From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9D7DD416849 for ; Fri, 31 Jul 2026 14:41:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785508903; cv=none; b=jr60mBeci8GIOnM39UtvkzJggGbwB6eszgKS+jG1jOwAGOjjZVjYTkD1t61UUwCbSXOsdDQYHzq3GEdedaaJNCr0LHxfAzAwZPa20apKmjhb5d4a3QDthX5MWbOG81WeFjwv4gsDKK4Gx80qN1//DCY0skeCFGjPP2E2UMbMmAA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785508903; c=relaxed/simple; bh=676jVp12RghrOPwzFXm6M05kWpCuXVi5gGt6A+m8Wbk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ex23TK77u7N/JAnsMkqJ7UYfDNjkdDQH9inZeFk97DZbbplhBI8wZn/ZcOY7qJ7irLwqCT1GE4V2tN1cCqBt688CGCsbvPPTqZhztbhkfVjWjO8dtn4iBTPK8hlIYA1PBHfRQxT8HN48CsYuBi5JkIlkB0Oe20z81tm3Wu4JKdk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=rcWDgzN7; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="rcWDgzN7" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E3EE204C; Fri, 31 Jul 2026 07:41:36 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E21943F86F; Fri, 31 Jul 2026 07:41:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785508900; bh=676jVp12RghrOPwzFXm6M05kWpCuXVi5gGt6A+m8Wbk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=rcWDgzN7DaT98KKU6d9Tmxtar5LyOjNZpeu5BcDU7/tzFus9k6ofiWPauqW/8XvLE o2zf4y4Lxspwp7UsYuEKgYe8M+rxOLVPdiXIW2N/AB9Ux/gg7ESj83V6Ou60SpO5DU Hh1+dqSW5BT42uHBWor2NrN/HNhSOBjY3KXtPu/A= Date: Fri, 31 Jul 2026 15:41:32 +0100 From: Mark Rutland To: Hongyan Xia Cc: Will Deacon , Masami Hiramatsu , Catalin Marinas , Jiazi Li , Pu Hu , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [RFC PATCH 1/9] arm64/entry: Bound certain debug exception paths in instrumentation windows Message-ID: References: <38af667517b99785ccbc2075f53a364ba2acc73c.1785153469.git.hongyan.xia@transsion.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <38af667517b99785ccbc2075f53a364ba2acc73c.1785153469.git.hongyan.xia@transsion.com> On Mon, Jul 27, 2026 at 12:25:34PM +0000, Hongyan Xia wrote: > From: Hongyan Xia > > The el1 debug exception handlers are noinstr, but their payload calls > (do_breakpoint(), do_watchpoint(), try_step_suspended_breakpoints() > and the Cortex-A76 erratum handler) are ordinary instrumentable code. > > Mark the boundaries explicitly with instrumentation_begin()/end(), in > the same style as x86 exception entries. > > The BRK handlers (do_el1_brk64(), do_el1_softstep()) will be dealt with > in later patches. > > Signed-off-by: Hongyan Xia Please don't do this. The instrumentation_{begin,end}() markers don't do anything useful on arm64 (since we don't use objtoo, etc), and adding them to a subset of arm64's exception entry code gives the misleading impression that these cases are different from other exception entry cases. Mark. > --- > arch/arm64/kernel/entry-common.c | 19 +++++++++++++++++-- > 1 file changed, 17 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/entry-common.c b/arch/arm64/kernel/entry-common.c > index ceb4eb11232a..466529cce1c3 100644 > --- a/arch/arm64/kernel/entry-common.c > +++ b/arch/arm64/kernel/entry-common.c > @@ -6,6 +6,7 @@ > */ > > #include > +#include > #include > #include > #include > @@ -380,7 +381,9 @@ static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr) > > state = arm64_enter_el1_dbg(regs); > debug_exception_enter(regs); > + instrumentation_begin(); > do_breakpoint(esr, regs); > + instrumentation_end(); > debug_exception_exit(regs); > arm64_exit_el1_dbg(regs, state); > } > @@ -388,9 +391,15 @@ static void noinstr el1_breakpt(struct pt_regs *regs, unsigned long esr) > static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr) > { > irqentry_state_t state; > + bool handled; > > state = arm64_enter_el1_dbg(regs); > - if (!cortex_a76_erratum_1463225_debug_handler(regs)) { > + > + instrumentation_begin(); > + handled = cortex_a76_erratum_1463225_debug_handler(regs); > + instrumentation_end(); > + > + if (!handled) { > debug_exception_enter(regs); > /* > * After handling a breakpoint, we suspend the breakpoint > @@ -398,7 +407,11 @@ static void noinstr el1_softstp(struct pt_regs *regs, unsigned long esr) > * If we are stepping a suspended breakpoint there's nothing more to do: > * the single-step is complete. > */ > - if (!try_step_suspended_breakpoints(regs)) > + instrumentation_begin(); > + handled = try_step_suspended_breakpoints(regs); > + instrumentation_end(); > + > + if (!handled) > do_el1_softstep(esr, regs); > debug_exception_exit(regs); > } > @@ -413,7 +426,9 @@ static void noinstr el1_watchpt(struct pt_regs *regs, unsigned long esr) > > state = arm64_enter_el1_dbg(regs); > debug_exception_enter(regs); > + instrumentation_begin(); > do_watchpoint(far, esr, regs); > + instrumentation_end(); > debug_exception_exit(regs); > arm64_exit_el1_dbg(regs, state); > } > -- > 2.47.3 >