From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 55D5E3515E6 for ; Tue, 4 Aug 2026 15:00:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785855630; cv=none; b=Hjt3nXz5owHCMe2kmnKE9DX+GpVPquRL/+IYQ8yAyO1FrfzAfOHAl4jr2GGcKYMuoNYvFv+P3dHuZ37JGlvTs3em8rOKBgpKLx4OPZiE/EYAx44UjUI6tPU/HBa5tLnLXt2xro+FkJ28EfdQYeU/3+tEdeXixsVBmJaRRd/BA5o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785855630; c=relaxed/simple; bh=qod7nuIJK3LbjzJXK5Ak2BXjKVmEFuQMsxsXzJ/nVxk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=g9EIVa78MhrV/L7fL6P6/R2lXqQNrqmnilD3Cwv5pzovHD44Y23E1wOAnwiX2nC76op/KDkZ4YB9nrsaJY3NHNUUwuraOaCUyLSq0dII18tpOPhekcQv1DQvabEv++g+crceHL05Td9aaAS0YC4b1JmFlXnQ82NOFO0pB/c0sUA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZOPlBtqQ; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZOPlBtqQ" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7964D165C; Tue, 4 Aug 2026 08:00:22 -0700 (PDT) Received: from J2N7QTR9R3 (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B5B7A3F86F; Tue, 4 Aug 2026 08:00:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785855626; bh=qod7nuIJK3LbjzJXK5Ak2BXjKVmEFuQMsxsXzJ/nVxk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZOPlBtqQHjwHO/AFGn3qfSS0j0Yjza8S4K2a6Qp12zk+20cuWBdgDfENP5zclhCll d04iVhJNyTxtv3jmmIoz8EFwWMCUE6+6sRQL61NC4vGF0rkLNn8MqCLdpaGNmrdNbN UUihAUfArHhPhIoDxC3iZ0Dw1TAo4u3PnvsOeVbQ= Date: Tue, 4 Aug 2026 16:00:22 +0100 From: Mark Rutland To: David Laight Cc: linux-arm-kernel@lists.infradead.org, ada.coupriediaz@arm.com, ardb@kernel.org, catalin.marinas@arm.com, hca@linux.ibm.com, linux-kernel@vger.kernel.org, maz@kernel.org, peterz@infradead.org, ruanjinjie@huawei.com, vladimir.murzin@arm.com, will@kernel.org, yang@os.amperecomputing.com Subject: Re: [RFC PATCH 07/13] arm64: percpu: Implement preemptible read/write ops Message-ID: References: <20260728123859.2911495-1-mark.rutland@arm.com> <20260728123859.2911495-8-mark.rutland@arm.com> <20260728224755.59cfd22d@pumpkin> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260728224755.59cfd22d@pumpkin> On Tue, Jul 28, 2026 at 10:47:55PM +0100, David Laight wrote: > On Tue, 28 Jul 2026 13:38:53 +0100 > Mark Rutland wrote: > > > Use the PCPU GPR infrastructure to implement preemptible this_cpu_read() > > and this_cpu_write(). > ... > > #define this_cpu_write_1(pcp, val) \ > > - _pcp_protect(__percpu_write_8, pcp, (unsigned long)val) > > + _pcp_wrap(__percpu_write_8, pcp, (unsigned long)val) > > Not new, but does that end up sign extending 'val' which is likely > to be more expensive than zero extending it? > Using '(val) + 0u + 0ul' might generate better code in some cases. For the existing code, there's no {zero,sign}-extension in practice due to our calling convention (AAPCS64) and inlining. AAPCS64 specifies that when an N-bit valiue is allocated into a register, bits[N-1:0] contain the value, and bits[63:N] contain unspecified values. The existing __percpu_write_##sz() only consumes 'val' as a 'u##sz', so the compiler doesn't need to do anything with the upper bits (and in practice doesn't do anything), so long as __percpu_write_##sz() is inlined into its caller. The new __percpu_write_##sz() in this series doesn't cast 'val' back down to a 'u##sz', so there is some unnecessary extension. I'll fix that by taking 'val' as a 'u##sz' in the function prototype, which'll avoid extension regardless of inlining. > Just noticed it should be (unsigned long)(val) as well. > Otherwise this_cpu_write_n(pcp, -7 / 4) isn't going to DTRT. Yes, that's a latent bug, and we have at least one other case (this_cpu_and()) where we miss brackets. I'll fix those up as a preparatory patches. Mark.