From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B565743846C for ; Tue, 4 Aug 2026 13:17:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785849479; cv=none; b=RosgkZ5Kns1fmokyj+cwQ8DyHxPuRNODb3DFYNAV/ADIO9qvmCAHbl64UVEzTmFZ4Gg+TNizL0GOncwRBsZPkKJ17uXf9v147NLPPvkqfPqsj1hEYpSl1HNJx1cPEfVLWCxEOvELm3jlwQ3TbdWyksDq8ytD6ENJnHwsiYjMMbc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1785849479; c=relaxed/simple; bh=/bQrHpd5GKLdcJhoVyd+Fq5uT1flkb2RrHINoB1lrYk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=uhRGJgQHDVom3RU4ScRG/PqUg1XYNGZkUV+DztsfS+CxqzHgeG/RWIEzjgzIWcat8e9KjTdBlLr3BIn/AWm42Nex8+1B9kH64LCZSfNCpHLmrAKsvhrmuM0Go4tHCUkHvRDHZgHPGx+3SddRdJ3n2+RPAteZ4qgKjyPEP0JX4Qk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=a+2tuoyC; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="a+2tuoyC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 588A91F000E9; Tue, 4 Aug 2026 13:17:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785849477; bh=I/xJUBIsf5tc/tiVs7VEOF8KlHKQaO0v8ZsALjsK6og=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=a+2tuoyCeQfldI1lbv6MGEskpRSxVFaek1rvE5zs6SOcwXL9xKDw+tEuVnDiHDdIR NVgUel9QhOsqPS5SwqYlDWQzIg2OJxf/DPJYni3VAS/5jGCzOqmUT8+0qNmAfJnWgy 9q25hWpEjcOSni+DpEOYl15ZC6B7IMkcwjMPxBk79qp1y4MwpdvCnGP0jbJeUWOK5v DJROoZnm7RyRJ4TqD60ij4VYaSGdXUAw8INMu7IL7uXe5lN9KLC/OgRe2UjD4e2pD1 YsHiWuGiL8wZ9Urqq686JdnSV7/X3NJfIPbwGcywnuYVXrlFwEvozsWvugkbxCBFAK qtCcGxIv1B8sA== Date: Tue, 4 Aug 2026 14:17:52 +0100 From: Will Deacon To: Bradley Morgan Cc: catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] arm64: sleep: factor sleep_save_stash slot lookup into a macro Message-ID: References: <20260717114746.15109-1-include@grrlz.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260717114746.15109-1-include@grrlz.net> On Fri, Jul 17, 2026 at 11:47:46AM +0000, Bradley Morgan wrote: > Both __cpu_suspend_enter() and _cpu_resume() open code the same > MPIDR_EL1 hash lookup to find the current CPU's slot in > sleep_save_stash. Factor it into a get_sleep_stash_slot > macro. > > Since that macro would be the only remaining user of > compute_mpidr_hash, inline the hash computation into > get_sleep_stash_slot and just remove compute_mpidr_hash > altogether. > > No functional change intended. > > Signed-off-by: Bradley Morgan > --- > Changes since V1: > - Inline the macro, there only is one user. (Will) > - Also change the C psuedocode to be correct > > arch/arm64/kernel/sleep.S | 103 +++++++++++++++----------------------- > 1 file changed, 41 insertions(+), 62 deletions(-) > > diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S > index f093cdf71be1..dcf00a4d6233 100644 > --- a/arch/arm64/kernel/sleep.S > +++ b/arch/arm64/kernel/sleep.S > @@ -7,48 +7,48 @@ > > .text > /* > - * Implementation of MPIDR_EL1 hash algorithm through shifting > + * Compute the address of the current CPU's entry in sleep_save_stash, > + * i.e. &sleep_save_stash[hash(MPIDR_EL1)], where the hash is an > + * implementation of the MPIDR_EL1 hash algorithm through shifting > * and OR'ing. > * > - * @dst: register containing hash result > - * @rs0: register containing affinity level 0 bit shift > - * @rs1: register containing affinity level 1 bit shift > - * @rs2: register containing affinity level 2 bit shift > - * @rs3: register containing affinity level 3 bit shift > - * @mpidr: register containing MPIDR_EL1 value > - * @mask: register containing MPIDR mask > - * > * Pseudo C-code: > * > - *u32 dst; > + * u64 mpidr = MPIDR_EL1 & mpidr_hash.mask; > + * u32 hash = ((mpidr & 0xff) >> mpidr_hash.shift_aff[0]) | > + * ((mpidr & 0xff00) >> mpidr_hash.shift_aff[1]) | > + * ((mpidr & 0xff0000) >> mpidr_hash.shift_aff[2]) | > + * ((mpidr & 0xff00000000) >> mpidr_hash.shift_aff[3]); > + * slot = &sleep_save_stash[hash]; > + * > + * @slot: output register > * > - *compute_mpidr_hash(u32 rs0, u32 rs1, u32 rs2, u32 rs3, u64 mpidr, u64 mask) { > - * u32 aff0, aff1, aff2, aff3; > - * u64 mpidr_masked = mpidr & mask; > - * aff0 = mpidr_masked & 0xff; > - * aff1 = mpidr_masked & 0xff00; > - * aff2 = mpidr_masked & 0xff0000; > - * aff3 = mpidr_masked & 0xff00000000; > - * dst = (aff0 >> rs0 | aff1 >> rs1 | aff2 >> rs2 | aff3 >> rs3); > - *} > - * Input registers: rs0, rs1, rs2, rs3, mpidr, mask > - * Output register: dst > - * Note: input and output registers must be disjoint register sets > - (eg: a macro instance with mpidr = x1 and dst = x1 is invalid) > + * Clobbers: x2 - x8 > */ > - .macro compute_mpidr_hash dst, rs0, rs1, rs2, rs3, mpidr, mask > - and \mpidr, \mpidr, \mask // mask out MPIDR bits > - and \dst, \mpidr, #0xff // mask=aff0 > - lsr \dst ,\dst, \rs0 // dst=aff0>>rs0 > - and \mask, \mpidr, #0xff00 // mask = aff1 > - lsr \mask ,\mask, \rs1 > - orr \dst, \dst, \mask // dst|=(aff1>>rs1) > - and \mask, \mpidr, #0xff0000 // mask = aff2 > - lsr \mask ,\mask, \rs2 > - orr \dst, \dst, \mask // dst|=(aff2>>rs2) > - and \mask, \mpidr, #0xff00000000 // mask = aff3 > - lsr \mask ,\mask, \rs3 > - orr \dst, \dst, \mask // dst|=(aff3>>rs3) > + .macro get_sleep_stash_slot slot > + mrs x3, mpidr_el1 > + adr_l x2, mpidr_hash > + ldr x8, [x2, #MPIDR_HASH_MASK] > + /* > + * Following code relies on the struct mpidr_hash > + * members size. > + */ > + ldp w4, w5, [x2, #MPIDR_HASH_SHIFTS] > + ldp w6, w7, [x2, #(MPIDR_HASH_SHIFTS + 8)] > + and x3, x3, x8 // mask out MPIDR bits > + and x2, x3, #0xff // aff0 > + lsr x2, x2, x4 // hash = aff0 >> rs0 > + and x8, x3, #0xff00 // aff1 > + lsr x8, x8, x5 > + orr x2, x2, x8 // hash |= aff1 >> rs1 > + and x8, x3, #0xff0000 // aff2 > + lsr x8, x8, x6 > + orr x2, x2, x8 // hash |= aff2 >> rs2 > + and x8, x3, #0xff00000000 // aff3 > + lsr x8, x8, x7 > + orr x2, x2, x8 // hash |= aff3 >> rs3 > + ldr_l \slot, sleep_save_stash > + add \slot, \slot, x2, lsl #3 // slot = &sleep_save_stash[hash] nit: In the old code, rs0-rs3 were arguments to the macro. Now that you've removed those, the comments are stale. Will