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Wed, 5 Aug 2026 02:28:40 +0000 Date: Tue, 4 Aug 2026 19:28:31 -0700 From: Alison Schofield To: Srirangan Madhavan CC: Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , , , , Alex Williamson , , , Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , Subject: Re: [PATCH v10 05/12] cxl: Cache endpoint decoder settings during PCI enumeration Message-ID: References: <20260804192958.1823952-1-smadhavan@nvidia.com> <20260804192958.1823952-6-smadhavan@nvidia.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260804192958.1823952-6-smadhavan@nvidia.com> X-ClientProxiedBy: BYAPR21CA0001.namprd21.prod.outlook.com (2603:10b6:a03:114::11) To DS4PPF0BAC23327.namprd11.prod.outlook.com (2603:10b6:f:fc02::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PPF0BAC23327:EE_|DM6PR11MB4641:EE_ X-MS-Office365-Filtering-Correlation-Id: 69d9207b-93b6-4912-456a-08def29942fb X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|376014|1800799024|23010399003|18002099003|22082099003|4143699003|56012099006|11063799006|6133799003|10067099003; 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This > gives driver-free reset paths an early HDM snapshot while avoiding the > pre-resource-assignment window in PCI capability initialization. > > Use the CXL Register Locator BAR Indicator to find the component register > BAR, reject unassigned, disabled, or zero memory BAR resources before > temporarily enabling Memory Space, and restore the original PCI_COMMAND > value before returning. > > CXL core reuses and refreshes the same cache as decoders are committed or > reset, and retries cache setup during CXL HDM enumeration if the PCI > bus-add attempt did not publish a cache. Move the register helpers into > the built-in CONFIG_CXL_HDM set so the early cache path is available > without cxl_core, and keep the cxl-test mock core from building a > duplicate regs.o. > > Signed-off-by: Srirangan Madhavan > --- > drivers/cxl/core/Makefile | 3 +- > drivers/cxl/core/hdm.c | 13 +- > drivers/cxl/core/regs.c | 4 + > drivers/cxl/core/resource.c | 313 ++++++++++++++++++++++++++++++++++++ > drivers/pci/bus.c | 2 + > drivers/pci/probe.c | 2 + > include/cxl/cxl.h | 26 +++ > tools/testing/cxl/Kbuild | 1 - > 8 files changed, 360 insertions(+), 4 deletions(-) > snip > diff --git a/drivers/cxl/core/resource.c b/drivers/cxl/core/resource.c snip > +void pci_cxl_hdm_init(struct pci_dev *pdev) > +{ > + int rc; > + > + rc = __pci_cxl_hdm_init(pdev); > + if (rc && rc != -ENOTTY && rc != -ENODEV) > + pci_dbg(pdev, "CXL HDM cache init failed: %d\n", rc); > +} Needs: EXPORT_SYMBOL_FOR_MODULES(pci_cxl_hdm_init, "cxl_core"); Without that the modular build fails, CONFIG_CXL_BUS=m ERROR: modpost: "pci_cxl_hdm_init" [drivers/cxl/core/cxl_core.ko] undefined! To catch this: build with CONFIG_CXL_BUS=m, not =y. With =y, hdm.o and resource.o both land in vmlinux so the reference resolves at link time and the missing export is invisible. This failure masked the first one because modpost aborts before Module.symvers is written, reads a stale Module.symvers and make some erroneous complaints. And, FWIW, with this and the mock Kbuild fixup in Patch 1, the series passes the CXL unit tests. -- Alison