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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66acad2ade5sm7178798d50.7.2026.08.10.14.29.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Aug 2026 14:30:00 -0700 (PDT) Date: Mon, 10 Aug 2026 17:29:57 -0400 From: Brian Masney To: Yu-Chun Lin Cc: mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de, cylee12@realtek.com, jyanchou@realtek.com, afaerber@suse.com, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-realtek-soc@lists.infradead.org, james.tai@realtek.com, cy.huang@realtek.com, stanley_chang@realtek.com Subject: Re: [PATCH v12 08/11] clk: realtek: Add support for MMC-tuned PLL clocks Message-ID: References: <20260804163807.1285869-1-eleanor.lin@realtek.com> <20260804163807.1285869-9-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260804163807.1285869-9-eleanor.lin@realtek.com> User-Agent: Mutt/2.4.0 (2026-06-19) On Wed, Aug 05, 2026 at 12:38:04AM +0800, Yu-Chun Lin wrote: > From: Cheng-Yu Lee > > Add clk_pll_mmc_ops for enable/disable, prepare, rate control, and status > operations on MMC PLL clocks. > > Also add clk_pll_mmc_phase_ops to support phase get/set operations. > > Signed-off-by: Cheng-Yu Lee > Co-developed-by: Jyan Chou > Signed-off-by: Jyan Chou > Co-developed-by: Yu-Chun Lin > Signed-off-by: Yu-Chun Lin Reviewed-by: Brian Masney