From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4CA4E429CC4 for ; Tue, 11 Aug 2026 11:24:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786447468; cv=none; b=IVIS3X83HnbiZRF9Li+krKGEn3153iMh4SFOJ12TTCDhcsChhmGdXIq8O2j7E6pQQfRV8h7RXAegNk7t0OAThinXNo2v6EO4rsyd12ohbkpo7V5VqSypCNgzc4vpCAnKAhXD4PsvaVkVQZIMO+0Bu6u6putnA+RYUDIia6OAiFA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786447468; c=relaxed/simple; bh=NYpGbm+9Oa7JZ2R2kQAY4wtMcRPRZdIeqyoesAWpR7Q=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DFEHyczcLk3D6PolZmGrgg9leBAm5eRfL9FJhGoU1mjMlGt1ZF4asmELNSQDmmtsrswCmcbenIPA5kqEO2+FeftItnSVGeQdnqVyFsGw0TGJzZtqqq02Spr670HFLdl2gjn4Z8LkhgEQrvqtaLZqjjcgPqnlMQJi29B5hMV5qu8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PucfnLls; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PucfnLls" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15E361F000E9; Tue, 11 Aug 2026 11:24:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786447466; bh=AOlRdH/L92fb7OOyEUdkTjMrylhg++68RVW1YX5mrjg=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=PucfnLls9TjGXNjOI3mFfEldnHv1DViAqfpQ0uTVvPSXNUbvmG8qWZycxToZ/U/Y0 ffn43ED4fW0PZkmJ/wd7PrnKD9vZeZTUIKZpVZTE3Ue0KLhQV6kPHoGRFMFHIzGcpw kCAd+SfBAAK2JYbkyFbdGschAsqD2CAkqN5QblWrSoS9NrynFIlxNAKXE2G+e9rRvK kyFq8b30z4XajvPvX+CiYlnzAgUb7gYmiBemgoFr/3uHSvV2JRAN2e8rrcY2UKw93R l11azPzStzs0DIWW7kpM1W3PbqFZ5Iy+fotfAJ45oUyBdh+Fq4gOkw3hx3lO2nYbve xeVXWFuOLUn0A== Date: Tue, 11 Aug 2026 16:54:23 +0530 From: Vinod Koul To: Cristian Ciocaltea Cc: Manivannan Sadhasivam , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov , kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Sashiko , Diederik de Haas , Dmitry Baryshkov , Andy Yan Subject: Re: [PATCH v5 02/10] phy: rockchip: samsung-hdptx: Prevent divide-by-zero when computing clk rate Message-ID: References: <20260723-hdptx-clk-fixes-v5-0-8e786067865f@collabora.com> <20260723-hdptx-clk-fixes-v5-2-8e786067865f@collabora.com> <605f96b2-709c-49f6-9446-49ed3bff7d96@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <605f96b2-709c-49f6-9446-49ed3bff7d96@collabora.com> On 07-08-26, 17:19, Cristian Ciocaltea wrote: > Hi Mani, > > On 8/7/26 3:56 PM, Manivannan Sadhasivam wrote: > > On Thu, Jul 23, 2026 at 10:41:45PM +0300, Cristian Ciocaltea wrote: > >> Calculating 'sdm' fraction in rk_hdptx_phy_clk_calc_rate_from_pll_cfg() > >> could trigger a divide-by-zero, as it uses div_u64() with a denominator > >> read directly from hardware: the values ropll_hw.sdm_deno, > >> ropll_hw.sdc_deno, ropll_hw.sdc_n, and ropll_hw.sdc_num are populated > >> from PLL registers which, in theory, could be left by the bootloader > >> uninitialized/misconfigured. > >> > >> Provide the necessary sanitization to avoid trusting the hardware state. > >> > >> Reported-by: Sashiko > >> Closes: https://sashiko.dev/#/patchset/20260611-hdptx-clk-fixes-v3-0-67b1b0c00e16@collabora.com?part=1 > >> Fixes: 3481fc04d969 ("phy: rockchip: samsung-hdptx: Compute clk rate from PLL config") > >> Tested-by: Diederik de Haas # NanoPC-T6 LTS > >> Reviewed-by: Dmitry Baryshkov > >> Reviewed-by: Andy Yan > >> Signed-off-by: Cristian Ciocaltea > >> --- > >> drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 11 ++++++++--- > >> 1 file changed, 8 insertions(+), 3 deletions(-) > >> > >> diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > >> index 710603afff86..44e99343f249 100644 > >> --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > >> +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c > >> @@ -2270,10 +2270,15 @@ static u64 rk_hdptx_phy_clk_calc_rate_from_pll_cfg(struct rk_hdptx_phy *hdptx) > >> > >> fout = PLL_REF_CLK * ropll_hw.pms_mdiv; > >> if (ropll_hw.sdm_en) { > >> + val = 16U * ropll_hw.sdm_deno * > >> + (ropll_hw.sdc_deno * ropll_hw.sdc_n - ropll_hw.sdc_num); > >> + if (!val) { > >> + dev_dbg(hdptx->dev, "Invalid ROPLL hw state: deno == 0\n"); > > > > If the hardware state is invalid, why can't this be a hard failure? > > This is an internal helper called from the .recalc_rate clk_op, which tries to > compute the current rate by reading back the hardware state. > > Since .recalc_rate returns unsigned long, we cannot propagate errors to the > caller. However, per the clk_ops documentation, the driver is expected to > return 0 if it cannot figure out the rate. > > Moreover, this condition isn't really fatal, as it only means the PLL > configuration currently stored in hardware can't be translated into a rate. The > next .set_rate should program a valid configuration and help with the recovery. This is a good explanation which may not be obvious to everyone. I would think that it would be good idea to add a comment for this here -- ~Vinod