From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46E32310651 for ; Tue, 11 Aug 2026 16:31:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786465917; cv=none; b=qYmYY44f1X4EAVpCTNz1H99Xs2qPZcg7abLJandm1akLj4A9G/fv7+epc28AOmdhx4U96dHLOaghClkoH+eG4KvIfTkQeYmlbIvoYT+goHPTQdPysSN1bGyoULI3CVho+w7rUzwygKeiopZPGgwLqVXvJVqwcrc7+L1hZzq8IX4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786465917; c=relaxed/simple; bh=dvpPNb2dhghoztFdZbcW8y0jlaPiKvVGDIpFGZR5hso=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Oy9nbz4TP10uiBu43jvklRmg636zVp1HQSGhpvu7PXO8no89Z7aTrNJ5dBdnYyEMPq6SnBKEn/HraTENFCIaJK2FT1EKRx7lF+WC9Er3g14q+jsO1bPgrnsKKce+Fu36jfCeIEYRmvVXbjOOWgFZlcFe95KtilNyuqJweo1Fx5g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h+flfhO4; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h+flfhO4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AFEDF1F00A3D; Tue, 11 Aug 2026 16:31:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786465916; bh=bKX9RgsFiP1r7FApfoPALLGgJl9OMxZlavqohIlPsAc=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=h+flfhO4kYLTodQvAdAvjsxFMapmlLBH+q2EncdGl/XDF0OhaaZbOVFaesOAys1ge aX2qFssi6oUgUpQavsTbKNaHdudDjbn1dF9K3RB9i9QzIsigOXj0uepgPbhwkCMYRU eYj5sePqrFfE3B3bacvOWt07qHsPBtVfKrUeibEokZ/UBuqwE24Hdi1YG5xwcYF8eO 8Kw8fH/Yr16/pH1Szn1LjbiC1FfbCt+txlVL6Fh7p1CUKcuiztJkt699jSaIvWnrD+ VibcGSD5ahjgiu3CvKmXWJ5OmwAuGC2OrqpDT7xVrzwIjJzNJLoyiR9uDFvZrIRmac sXkEiZ2JZ+n5A== Date: Tue, 11 Aug 2026 18:31:52 +0200 From: Lorenzo Pieralisi To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , nd , "maz@kernel.org" Subject: Re: [PATCH v2 2/2] irqchip/gic-v5: Synchronize CPU interface disable Message-ID: References: <20260811152630.942023-1-sascha.bischoff@arm.com> <20260811152630.942023-3-sascha.bischoff@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260811152630.942023-3-sascha.bischoff@arm.com> On Tue, Aug 11, 2026 at 03:27:31PM +0000, Sascha Bischoff wrote: > The write disabling the GICv5 CPU interface is only guaranteed to take > effect after a context synchronization event. Without one, execution can > return from gicv5_cpu_disable_interrupts() while an interrupt is still > able to be taken. > > Add an ISB after the ICC_CR0_EL1 write to ensure interrupts are > disabled before the function returns. No corresponding ISB is added > when enabling the interface, as interrupt delivery is asynchronous and > there is no obvious benefit to waiting for it. > > Fixes: 7ec80fb3f025 ("irqchip/gic-v5: Add GICv5 PPI support") > Link: https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff@arm.com?part=6 > Signed-off-by: Sascha Bischoff > --- > drivers/irqchip/irq-gic-v5.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Lorenzo Pieralisi > diff --git a/drivers/irqchip/irq-gic-v5.c b/drivers/irqchip/irq-gic-v5.c > index e9d1795235a66..6a99c541b559b 100644 > --- a/drivers/irqchip/irq-gic-v5.c > +++ b/drivers/irqchip/irq-gic-v5.c > @@ -983,6 +983,7 @@ static void gicv5_cpu_disable_interrupts(void) > > cr0 = FIELD_PREP(ICC_CR0_EL1_EN, 0); > write_sysreg_s(cr0, SYS_ICC_CR0_EL1); > + isb(); > } > > static void gicv5_cpu_enable_interrupts(void) > -- > 2.34.1