From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C463233E37A for ; Tue, 25 Aug 2026 16:44:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787676262; cv=none; b=Ho6CIlTPnt9UiwESmkUwFuj5PuPBuutCpAj4s2d2op3UFp8lg+I3xMIPhmk17I579fIcRlhpk+K9rxtM8vt++4aUdMJYEkZdVvZxQaZ0jBhpXrr9uBWuxYWM+ljMOgNd/NDRuGzELiRP06HWF1SnNwDULyseLffTqrX2I734AV8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787676262; c=relaxed/simple; bh=8dujzqA2EJnJpCBIKHtWnkOqbBfvnVXF8kmsd51rOYA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=jeta4Cpaz4Ttxx5eGLdWUPwphWmHxkQVrmmKWm/7WF4yNUMrAmHFkpHN9S1gG/vfLUneakIVXRAhyxYjEdmMmcXLSHZMtssgECuuuEOFEDT2NRLzTDBKkZ8NSp0mjCd7mXbpoVmGfJq4r2t4/qLTTZ7pyFGebStYdH2A8W71h4k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lc5N3dWn; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lc5N3dWn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 216351F000E9; Tue, 25 Aug 2026 16:44:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787676261; bh=HhDnYJp6idU/zB/vpIZI1eo8XyX+VQJ6y+dK4kTg7es=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=lc5N3dWni19ze5u+0uMkDDn2EcJBmW8KejCOvedJ1G3bvff6VjTKA++o4r2/zX4ah pdXF7g5OKNCO26VzY76H8NWtdQ+AhxPhl2LKUn7KlfKzUOKR8d9/y0AhriYtro1GJA 1FhdvugucOPlDv6fTQ81FCQEQ3Q4ip4voc3N/T5lqkX8NhMXpmx2wtHePEjKcuhtRS IW5CRx8ruYhDfNNkjRwTgkZVpIp3X0B22RVLoKfGV7lhe+RMqRl1zSTniq2G1cZ5Dp j10p3MT+bnpNHHTLgz+knj6X6hsg14ZRrFXprL7IFZdoUAyfYpcjlOmugdUrxGN9nk NncWc4mFC4qHw== Date: Tue, 25 Aug 2026 17:44:14 +0100 From: Will Deacon To: "David Hildenbrand (Arm)" Cc: Xueyuan Chen , akpm@linux-foundation.org, ljs@kernel.org, usama.arif@linux.dev, catalin.marinas@arm.com, linux-arm-kernel@lists.infradead.org, tglx@kernel.org, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com, x86@kernel.org, hpa@zytor.com, rppt@kernel.org, ryan.roberts@arm.com, ziy@nvidia.com, baohua@kernel.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Lance Yang Subject: Re: [PATCH v6 2/3] arm64/mm: add set_direct_map_ro_noflush() Message-ID: References: <20260730090647.2401252-1-xueyuan.chen21@gmail.com> <20260730090647.2401252-3-xueyuan.chen21@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Aug 25, 2026 at 05:52:20PM +0200, David Hildenbrand (Arm) wrote: > On 7/30/26 11:06, Xueyuan Chen wrote: > > Implement set_direct_map_ro_noflush() for arm64 with update_range_prot() on > > the linear map, setting PTE_RDONLY and clearing PTE_WRITE. Keep the > > existing can_set_direct_map() guard and leave TLB invalidation to the > > caller. > > > > Co-developed-by: Lance Yang > > Signed-off-by: Lance Yang > > Signed-off-by: Xueyuan Chen > > --- > > arch/arm64/include/asm/set_memory.h | 2 ++ > > arch/arm64/mm/pageattr.c | 10 ++++++++++ > > 2 files changed, 12 insertions(+) > > > > diff --git a/arch/arm64/include/asm/set_memory.h b/arch/arm64/include/asm/set_memory.h > > index 90f61b17275e..7083260303c3 100644 > > --- a/arch/arm64/include/asm/set_memory.h > > +++ b/arch/arm64/include/asm/set_memory.h > > @@ -14,6 +14,8 @@ int set_memory_valid(unsigned long addr, int numpages, int enable); > > int set_direct_map_invalid_noflush(struct page *page); > > int set_direct_map_default_noflush(struct page *page); > > int set_direct_map_valid_noflush(struct page *page, unsigned nr, bool valid); > > +int set_direct_map_ro_noflush(const void *addr, unsigned long nr_pages); > > +#define set_direct_map_ro_noflush set_direct_map_ro_noflush > > bool kernel_page_present(struct page *page); > > > > int set_memory_encrypted(unsigned long addr, int numpages); > > diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c > > index ce035e1b4eaf..c51236b61651 100644 > > --- a/arch/arm64/mm/pageattr.c > > +++ b/arch/arm64/mm/pageattr.c > > @@ -365,6 +365,16 @@ int set_direct_map_valid_noflush(struct page *page, unsigned nr, bool valid) > > return set_memory_valid(addr, nr, valid); > > } > > > > +int set_direct_map_ro_noflush(const void *addr, unsigned long nr_pages) > > +{ > > + if (!can_set_direct_map()) > > + return 0; > > + > > + return update_range_prot((unsigned long)addr, PAGE_SIZE * nr_pages, > > + __pgprot(PTE_RDONLY), > > + __pgprot(PTE_WRITE)); > > +} > > + > > #ifdef CONFIG_DEBUG_PAGEALLOC > > /* > > * This is - apart from the return value - doing the same > > We'll need an ACK from arm64 maintaines. To me this looks good. I generally dislike deferring critical things like TLB invalidation to the caller, so it would be good to see an example of a caller that really needs that. The caller in patch 1 unconditionally calls flush_tlb_kernel_range() immediately after calling set_direct_map_ro_noflush(). In fact, that means we have a pointless invalidation if !can_set_direct_map(). See exhibit A :) Will