From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3E19947A861 for ; Tue, 18 Aug 2026 14:07:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787062073; cv=none; b=Fi5aOvGrMH++iOsFJlWTi/WGw7jUY/BZ1jwzcEl91BjVuTQiI83sI4gzuOJ3CLbnZNU45424KGr2VqLZJGcavlsxIts9nYchfVHbHcZL5o3z/HMOxygtdzEhmpFFpful3bwm6O3CSYx0l1eN25W4DhAoQPzuZQAl3LroFcC7Wvs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787062073; c=relaxed/simple; bh=XYnpofG5ApFYBdgBh7eiqhDJLh9ipL/B1jlA8wAAIas=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=oPfzO9BujEs7AaXOqfaP4Go00absvpjH0sVTZmhDFX3R8+3Y07U5OYBcWNRw5+KPzJOobf3RAfGDmcxdEeUq28D+LJD8pMogfyvJye65lToD7H/nHj2XJgiliT73GFywC70/s7LGON2nNZNZlNEbfuxHE3Xo0DUzY6RUhQ917SE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=jlQrt93o; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="jlQrt93o" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 44278152B; Tue, 18 Aug 2026 07:07:46 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 187C43F85F; Tue, 18 Aug 2026 07:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1787062070; bh=XYnpofG5ApFYBdgBh7eiqhDJLh9ipL/B1jlA8wAAIas=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jlQrt93omVnNUGW5AJAWkmrhdAxdJUeYlENyL9uf3jbP9mEjIJbPbVHtQ8AbK/8XQ qBdKSDBteuuzyBA4Km/Yh2uL4pt+s6L1zOxsmN2ydh8aCItQsF1z7h81P3Gf7S8WvB wrjfJAgW8ba8u3QAJm4YaQLsE0ncWlqwcTgwpqOg= Date: Tue, 18 Aug 2026 15:07:45 +0100 From: Catalin Marinas To: James Houghton Cc: Will Deacon , Muchun Song , Oscar Salvador , Nikos Nikoleris , Linu Cherian , Mark Rutland , David Hildenbrand , Andrew Morton , Ryan Roberts , Nanyong Sun , Yu Zhao , Frank van der Linden , David Rientjes , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org Subject: Re: [PATCH 07/18] arm64: Add system_supports_hvo Message-ID: References: <20260708031129.3503195-1-jthoughton@google.com> <20260708031129.3503195-8-jthoughton@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260708031129.3503195-8-jthoughton@google.com> On Wed, Jul 08, 2026 at 03:11:17AM +0000, James Houghton wrote: > diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h > index 25c61cda901c..6db3ef827f86 100644 > --- a/arch/arm64/include/asm/cpucaps.h > +++ b/arch/arm64/include/asm/cpucaps.h > @@ -75,6 +75,8 @@ cpucap_is_possible(const unsigned int cap) > return IS_ENABLED(CONFIG_HW_PERF_EVENTS); > case ARM64_HAS_LSUI: > return IS_ENABLED(CONFIG_ARM64_LSUI); > + case ARM64_HVO_COMPATIBLE: > + return IS_ENABLED(CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP); > } We shouldn't use HVO, a software feature, as a CPU capability name, even if it's called HVO_COMPATIBLE. Maybe we can come up with a hardware related name, e.g. BBM_THROUGH_AF. > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 9a22df0c5120..3b9224b99a5f 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -2172,6 +2172,16 @@ static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int sco > return cpu_supports_bbml2_noabort(); > } > > +static bool hvo_compatible(const struct arm64_cpu_capabilities *caps, int scope) > +{ > + /* > + * We need BBML2 to support Block -> Table transitions without taking > + * faults, and we need HW AF support to support changing the OA without > + * taking faults. > + */ > + return cpu_supports_bbml2_noabort() && supports_hw_af(scope); > +} I think this is wrong. cpu_supports_bbml2_noabort() only checks the current CPU while hvo_compatible() will be run once on the sanitised register values (SCOPE_SYSTEM). I should be something like: cpus_have_cap(ARM64_HAS_BBML2_NOABORT) && supports_hw_af(scope) -- Catalin