From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 188EE18A6CF for ; Tue, 18 Aug 2026 14:16:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787062582; cv=none; b=cThZ5/Wa1xbpM0x9JDWJal0K+e293NSg/3dXG3MsUidVBCuYEnGSPPAEfWkaHlf8x9VMyRb9Q5x0Bl0jcP6DHGs04yYpK2hLttpg1tkpDMkbk2WG1TpxPR7wAsofmjWYxkE4DZB/U+Nh3Q+gOWCUU68j1yUIQH9NtbexGF9cmyc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787062582; c=relaxed/simple; bh=n2wKaJ7B0u+TOzRiWJjt2/jNzta6bxVIi/vLveRb+xM=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=aFCTUttn8B8+j6Tns171H2xNMEVNcIizMyC/kZp8l5va4LOSxGeQpCA2eDnwoiERgv2nBI8BfXBWQSX7nZ1HNCuLktWehSI9BL2D8Nd2BtHKgzLGzcTsF1cZMQNyY00qz43lulg+Q8X/eYrDNwUnTZ8ITwu0XSK/DPADPlp4RuA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=EhPcYTo2; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="EhPcYTo2" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AEEEF1516; Tue, 18 Aug 2026 07:16:16 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 872973F85F; Tue, 18 Aug 2026 07:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1787062580; bh=n2wKaJ7B0u+TOzRiWJjt2/jNzta6bxVIi/vLveRb+xM=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=EhPcYTo21sYUZH9+m6BG3jc3jRms3MDajrKqMQo3+J/Br/TT7Bx5wZisHVwYpinRs vNmVPG9EUiMlKE4qll0V0DRk3wH2LxO3ltS9xRWlXNM6ILTsIElFg6wNQGUWdjxH6M kKgzNHLQgUyEWcTSuxQrpZEPjKeGAT6HYZ7x/QZs= Date: Tue, 18 Aug 2026 15:16:07 +0100 From: Catalin Marinas To: James Houghton Cc: Will Deacon , Muchun Song , Oscar Salvador , Nikos Nikoleris , Linu Cherian , Mark Rutland , David Hildenbrand , Andrew Morton , Ryan Roberts , Nanyong Sun , Yu Zhao , Frank van der Linden , David Rientjes , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mm@kvack.org Subject: Re: [PATCH 10/18] arm64: Support hugetlb vmemmap optimization Message-ID: References: <20260708031129.3503195-1-jthoughton@google.com> <20260708031129.3503195-11-jthoughton@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260708031129.3503195-11-jthoughton@google.com> On Wed, Jul 08, 2026 at 03:11:20AM +0000, James Houghton wrote: > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b3afe0688919..cf4bd6bd7f11 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -259,6 +259,7 @@ config ARM64 > select USER_STACKTRACE_SUPPORT > select VDSO_GETRANDOM > select VMAP_STACK > + select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if ARM64_WANT_OPTIMIZE_HUGETLB_VMEMMAP Nit: we try to keep this list alphabetically ordered. > help > ARM 64-bit (AArch64) Linux support. > > @@ -1607,6 +1608,17 @@ config ARCH_SPARSEMEM_ENABLE > def_bool y > select SPARSEMEM_VMEMMAP_ENABLE > > +config ARM64_WANT_OPTIMIZE_HUGETLB_VMEMMAP > + bool "Enable support for HugeTLB Vmemmap Optimization (HVO)" > + default n Nit: 'n' is the default already. > + depends on HUGETLB_PAGE && SPARSEMEM_VMEMMAP && ARM64_HW_AFDBM > + help > + Enable support for HVO. When enabled, late-onlining of CPUs that do I'd drop 'of', not sure how it reads better. Maybe just 'late CPUs ... will not be onlined'. > + not support features required by HVO will not be onlined if all boot > + CPUs do have such support. > + > + If unsure, say N > + > config HW_PERF_EVENTS > def_bool y > depends on ARM_PMU -- Catalin