From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E62E83909A3 for ; Sat, 22 Aug 2026 21:40:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787434822; cv=none; b=WKitGsVvaYAR6WRxq8w0Q9cT+b5pIXIqBKHtVKTvBsw3bbM3cybqbFfuMy4KoJKcWciAWgzNxfHl2qpA3AEPIkd9RNxPaSmB864SfE85TRtxU+4SyIwR+RfgJ5Ict4ydBA8O/WT++FaDY9+12lCaMqClUaThcHsj/WCpGqxgtgw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1787434822; c=relaxed/simple; bh=o7kBqDjlsLvUHkkz3N8X2KAJ5n1w9DodKhYD32TGR8I=; h=Date:From:To:Cc:Subject:Message-ID:MIME-Version:Content-Type: Content-Disposition; b=TDkIM5AmTiu3Ujzwc7NoFcbycijsR+YLBpYffI5SJFoZlk90srAXo2SL6+MtYjnZUQzowFFDEE/TBQixDPA9IUAm6gNx1WnZvgZ03c1xN1FbTpZesUJ2q1OhYGFhTwHTRTz1YT/R/RPFYYkASFjZ36uSUomCsVDctU2oGHRXdYo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=MPfGiprX; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="MPfGiprX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0E3BE1F000E9; Sat, 22 Aug 2026 21:40:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1787434817; bh=06KXnLkvDgqAjvqovrzBE6JUcRE+agVy9Ve+vUdbeyc=; h=Date:From:To:Cc:Subject; b=MPfGiprX7xajQoku2u0ncEHwwzG3r0VgEFi2EvqRGBcLxTT9RkOiIxWLyUopMBySj AEKT6uWqlQxrKq537/3CuFCPZZssIuzHsg+KVwhZEvzV1JxOV4bWerq5QY7MgLkKNH TyPaFgWOKuD06W4+43C+zcrJXmf9rDfgLB6Ghjb0nhzJz7Zfo3kz+2+p/g5ha+UGLm zqO2Y+9UyJRRDgI9/pP/8sZ0TF4uXxXKNcU1/BGmWKXTJYeCR8Ahh9ivaWf1ifhvGD jodsKKC+/syTzQThUAZeA6Wh+CiYPDKhbDm2F6NyT65Y8JYzMYd+s5VEPn82gZTDyq qq5s2y+yqajvg== Date: Sat, 22 Aug 2026 23:40:13 +0200 From: Ingo Molnar To: Linus Torvalds Cc: linux-kernel@vger.kernel.org, Thomas Gleixner , Peter Zijlstra Subject: [GIT PULL] IRQ fixes Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Linus, Please pull the latest irq/urgent Git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq-urgent-2026-08-22 for you to fetch changes up to 58b34b72b64bfbfc5f8ad4d8f229942aff76597e: Miscellaneous irqchip driver fixes: - Fix potential loss of interrupt in the renesas-rzg2l irqchip driver (Biju Das) - Fix a series of mostly corner case & error handling bugs in the gic-v5 irqchip driver (Lorenzo Pieralisi) - Fix hardware probing on the ast2700-intc irqchip driver (Michael Pesa) - Fix endianness bug on the Realtek Interrupt Controller (Rustam Adilov) - Fix incorrect sleeping allocation in critical section in the ast2700-intc irqchip driver (Ryan Chen) - Fix two bugs in the GICv5 irqchip driver: clear IRQ affinity properly on teardown, and fix IRQ serialization bug on disabling the IRQ (Sascha Bischoff) Thanks, Ingo ------------------> Biju Das (1): irqchip/renesas-rzg2l: Fix loss of interrupt Lorenzo Pieralisi (7): irqchip/gic-v5: Check get_logical_index() return value in MADT IAFFID parsing irqchip/gic-v5: Check for NULL LPI domain on domain teardown irqchip/gic-v5: Disable IRSes on probe failures irqchip/gic-v5: Fix gicv5_init_common() error paths irqchip/gic-v5: Release IRS iomem region on driver init failure irqchip/gic-v5: Use logical cpu 0 irs_data for dynamic IST allocation irqchip/gic-v5: Defer default SPI and LPI IAFFID programming Michael Pesa (1): irqchip/ast2700-intc: Disable all interrupt merge banks on probe Rustam Adilov (1): irqchip/irq-realtek-rtl: Use readl_be()/writel_be() instead of readl()/writel() Ryan Chen (1): irqchip/ast2700-intc: Avoid allocating in the irq_domain activate() callback Sascha Bischoff (2): irqchip/gic-v5: Clear per-CPU IRS data on teardown irqchip/gic-v5: Synchronize CPU interface disable drivers/irqchip/irq-ast2700-intc0.c | 4 ++-- drivers/irqchip/irq-ast2700-intc1.c | 3 ++- drivers/irqchip/irq-gic-v5-irs.c | 38 ++++++++++++++++++++++++++++++++++++- drivers/irqchip/irq-gic-v5.c | 29 ++++++++++++---------------- drivers/irqchip/irq-realtek-rtl.c | 20 ++++++++++++------- drivers/irqchip/irq-renesas-rzg2l.c | 4 ++-- include/linux/irqchip/arm-gic-v5.h | 2 ++ 7 files changed, 70 insertions(+), 30 deletions(-)