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Mon, 24 Aug 2026 19:30:30 +0000 Date: Mon, 24 Aug 2026 15:30:25 -0400 From: Rodrigo Vivi To: Heikki Krogerus CC: Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , Raag Jadav , Mika Westerberg , Andy Shevchenko , Andi Shyti , Ramesh Babu B , "Michael J. Ruhl" , , , Subject: Re: [PATCH v7 1/3] i2c: designware: Global register definitions Message-ID: References: <20260811121008.1493015-1-heikki.krogerus@linux.intel.com> <20260811121008.1493015-2-heikki.krogerus@linux.intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260811121008.1493015-2-heikki.krogerus@linux.intel.com> X-ClientProxiedBy: SJ0PR13CA0059.namprd13.prod.outlook.com (2603:10b6:a03:2c2::34) To IA0PR11MB7752.namprd11.prod.outlook.com (2603:10b6:208:442::20) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA0PR11MB7752:EE_|CH0PR11MB8168:EE_ X-MS-Office365-Filtering-Correlation-Id: 89e99406-b254-4bca-1285-08df02162897 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|376014|10067099003|56012099006|4143699003|11063799006|18002099003|22082099003|3023799007; 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That removes the need to > duplicate them in the adaptation layers for this driver > outside of drivers/i2c/busses/. There is at least one of > those in drivers/gpu/drm/xe/xe_i2c.c. > > Suggested-by: Andy Shevchenko > Suggested-by: Raag Jadav > Reviewed-by: Raag Jadav > Reviewed-by: Mika Westerberg > Reviewed-by: Andy Shevchenko Andi, Mika, are you okay to get this merged through drm-xe-next? Thanks, Rodrigo. > Signed-off-by: Heikki Krogerus > --- > MAINTAINERS | 1 + > drivers/i2c/busses/i2c-designware-common.c | 2 + > drivers/i2c/busses/i2c-designware-core.h | 85 +--------------- > drivers/i2c/busses/i2c-designware-master.c | 2 + > drivers/i2c/busses/i2c-designware-slave.c | 2 + > include/linux/designware_i2c.h | 107 +++++++++++++++++++++ > 6 files changed, 116 insertions(+), 83 deletions(-) > create mode 100644 include/linux/designware_i2c.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 928b3ba23a76b..1d0685b2cfdb0 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -26253,6 +26253,7 @@ R: Andy Shevchenko > L: linux-i2c@vger.kernel.org > S: Supported > F: drivers/i2c/busses/i2c-designware-* > +F: include/linux/designware_i2c.h > > SYNOPSYS DESIGNWARE I2C DRIVER - AMDISP > M: Nirujogi Pratap > diff --git a/drivers/i2c/busses/i2c-designware-common.c b/drivers/i2c/busses/i2c-designware-common.c > index e4dfa2ec58bb7..a1eca6cd4b75e 100644 > --- a/drivers/i2c/busses/i2c-designware-common.c > +++ b/drivers/i2c/busses/i2c-designware-common.c > @@ -33,6 +33,8 @@ > #include > #include > > +#include > + > #include "i2c-designware-core.h" > > #define DW_IC_DEFAULT_BUS_CAPACITANCE_pF 100 > diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h > index c71aa2dd368d5..2c929a6e8da2a 100644 > --- a/drivers/i2c/busses/i2c-designware-core.h > +++ b/drivers/i2c/busses/i2c-designware-core.h > @@ -18,6 +18,8 @@ > #include > #include > > +#include > + > #define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \ > I2C_FUNC_SMBUS_BYTE | \ > I2C_FUNC_SMBUS_BYTE_DATA | \ > @@ -25,23 +27,6 @@ > I2C_FUNC_SMBUS_BLOCK_DATA | \ > I2C_FUNC_SMBUS_I2C_BLOCK) > > -#define DW_IC_CON_MASTER BIT(0) > -#define DW_IC_CON_SPEED_STD (1 << 1) > -#define DW_IC_CON_SPEED_FAST (2 << 1) > -#define DW_IC_CON_SPEED_HIGH (3 << 1) > -#define DW_IC_CON_SPEED_MASK GENMASK(2, 1) > -#define DW_IC_CON_10BITADDR_SLAVE BIT(3) > -#define DW_IC_CON_10BITADDR_MASTER BIT(4) > -#define DW_IC_CON_RESTART_EN BIT(5) > -#define DW_IC_CON_SLAVE_DISABLE BIT(6) > -#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) > -#define DW_IC_CON_TX_EMPTY_CTRL BIT(8) > -#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) > -#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11) > - > -#define DW_IC_DATA_CMD_DAT GENMASK(7, 0) > -#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) > - > /* > * Register access parameters > */ > @@ -55,65 +40,9 @@ > #define DW_IC_FIFO_RX_FIELD GENMASK(15, 8) > #define DW_IC_FIFO_MIN_DEPTH 2 > > -/* > - * Registers offset > - */ > -#define DW_IC_CON 0x00 > -#define DW_IC_TAR 0x04 > -#define DW_IC_SAR 0x08 > -#define DW_IC_DATA_CMD 0x10 > -#define DW_IC_SS_SCL_HCNT 0x14 > -#define DW_IC_SS_SCL_LCNT 0x18 > -#define DW_IC_FS_SCL_HCNT 0x1c > -#define DW_IC_FS_SCL_LCNT 0x20 > -#define DW_IC_HS_SCL_HCNT 0x24 > -#define DW_IC_HS_SCL_LCNT 0x28 > -#define DW_IC_INTR_STAT 0x2c > -#define DW_IC_INTR_MASK 0x30 > -#define DW_IC_RAW_INTR_STAT 0x34 > -#define DW_IC_RX_TL 0x38 > -#define DW_IC_TX_TL 0x3c > -#define DW_IC_CLR_INTR 0x40 > -#define DW_IC_CLR_RX_UNDER 0x44 > -#define DW_IC_CLR_RX_OVER 0x48 > -#define DW_IC_CLR_TX_OVER 0x4c > -#define DW_IC_CLR_RD_REQ 0x50 > -#define DW_IC_CLR_TX_ABRT 0x54 > -#define DW_IC_CLR_RX_DONE 0x58 > -#define DW_IC_CLR_ACTIVITY 0x5c > -#define DW_IC_CLR_STOP_DET 0x60 > -#define DW_IC_CLR_START_DET 0x64 > -#define DW_IC_CLR_GEN_CALL 0x68 > -#define DW_IC_ENABLE 0x6c > -#define DW_IC_STATUS 0x70 > -#define DW_IC_TXFLR 0x74 > -#define DW_IC_RXFLR 0x78 > -#define DW_IC_SDA_HOLD 0x7c > -#define DW_IC_TX_ABRT_SOURCE 0x80 > -#define DW_IC_ENABLE_STATUS 0x9c > -#define DW_IC_CLR_RESTART_DET 0xa8 > -#define DW_IC_SMBUS_INTR_MASK 0xcc > -#define DW_IC_COMP_PARAM_1 0xf4 > -#define DW_IC_COMP_VERSION 0xf8 > #define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */ > -#define DW_IC_COMP_TYPE 0xfc > #define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */ > > -#define DW_IC_INTR_RX_UNDER BIT(0) > -#define DW_IC_INTR_RX_OVER BIT(1) > -#define DW_IC_INTR_RX_FULL BIT(2) > -#define DW_IC_INTR_TX_OVER BIT(3) > -#define DW_IC_INTR_TX_EMPTY BIT(4) > -#define DW_IC_INTR_RD_REQ BIT(5) > -#define DW_IC_INTR_TX_ABRT BIT(6) > -#define DW_IC_INTR_RX_DONE BIT(7) > -#define DW_IC_INTR_ACTIVITY BIT(8) > -#define DW_IC_INTR_STOP_DET BIT(9) > -#define DW_IC_INTR_START_DET BIT(10) > -#define DW_IC_INTR_GEN_CALL BIT(11) > -#define DW_IC_INTR_RESTART_DET BIT(12) > -#define DW_IC_INTR_MST_ON_HOLD BIT(13) > - > #define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \ > DW_IC_INTR_TX_ABRT | \ > DW_IC_INTR_STOP_DET) > @@ -123,16 +52,6 @@ > DW_IC_INTR_RX_UNDER | \ > DW_IC_INTR_RD_REQ) > > -#define DW_IC_ENABLE_ENABLE BIT(0) > -#define DW_IC_ENABLE_ABORT BIT(1) > - > -#define DW_IC_STATUS_ACTIVITY BIT(0) > -#define DW_IC_STATUS_TFE BIT(2) > -#define DW_IC_STATUS_RFNE BIT(3) > -#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) > -#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) > -#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7) > - > #define DW_IC_SDA_HOLD_RX_SHIFT 16 > #define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16) > > diff --git a/drivers/i2c/busses/i2c-designware-master.c b/drivers/i2c/busses/i2c-designware-master.c > index 7a301c8b604ef..a1bcc3797e4ff 100644 > --- a/drivers/i2c/busses/i2c-designware-master.c > +++ b/drivers/i2c/busses/i2c-designware-master.c > @@ -25,6 +25,8 @@ > #include > #include > > +#include > + > #include "i2c-designware-core.h" > > #define AMD_TIMEOUT_MIN_US 25 > diff --git a/drivers/i2c/busses/i2c-designware-slave.c b/drivers/i2c/busses/i2c-designware-slave.c > index ad0d5fbfa6d5e..0abcc7757b231 100644 > --- a/drivers/i2c/busses/i2c-designware-slave.c > +++ b/drivers/i2c/busses/i2c-designware-slave.c > @@ -19,6 +19,8 @@ > #include > #include > > +#include > + > #include "i2c-designware-core.h" > > int i2c_dw_reg_slave(struct i2c_client *slave) > diff --git a/include/linux/designware_i2c.h b/include/linux/designware_i2c.h > new file mode 100644 > index 0000000000000..53f37f18a7229 > --- /dev/null > +++ b/include/linux/designware_i2c.h > @@ -0,0 +1,107 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Synopsys DesignWare I2C register definitions > + * > + * Copyright (C) 2026, Intel Corporation > + */ > + > +#ifndef __LINUX_DESIGNWARE_I2C_H > +#define __LINUX_DESIGNWARE_I2C_H > + > +#include > + > +/* > + * Registers offset > + */ > +#define DW_IC_CON 0x00 > +#define DW_IC_TAR 0x04 > +#define DW_IC_SAR 0x08 > +#define DW_IC_DATA_CMD 0x10 > +#define DW_IC_SS_SCL_HCNT 0x14 > +#define DW_IC_SS_SCL_LCNT 0x18 > +#define DW_IC_FS_SCL_HCNT 0x1c > +#define DW_IC_FS_SCL_LCNT 0x20 > +#define DW_IC_HS_SCL_HCNT 0x24 > +#define DW_IC_HS_SCL_LCNT 0x28 > +#define DW_IC_INTR_STAT 0x2c > +#define DW_IC_INTR_MASK 0x30 > +#define DW_IC_RAW_INTR_STAT 0x34 > +#define DW_IC_RX_TL 0x38 > +#define DW_IC_TX_TL 0x3c > +#define DW_IC_CLR_INTR 0x40 > +#define DW_IC_CLR_RX_UNDER 0x44 > +#define DW_IC_CLR_RX_OVER 0x48 > +#define DW_IC_CLR_TX_OVER 0x4c > +#define DW_IC_CLR_RD_REQ 0x50 > +#define DW_IC_CLR_TX_ABRT 0x54 > +#define DW_IC_CLR_RX_DONE 0x58 > +#define DW_IC_CLR_ACTIVITY 0x5c > +#define DW_IC_CLR_STOP_DET 0x60 > +#define DW_IC_CLR_START_DET 0x64 > +#define DW_IC_CLR_GEN_CALL 0x68 > +#define DW_IC_ENABLE 0x6c > +#define DW_IC_STATUS 0x70 > +#define DW_IC_TXFLR 0x74 > +#define DW_IC_RXFLR 0x78 > +#define DW_IC_SDA_HOLD 0x7c > +#define DW_IC_TX_ABRT_SOURCE 0x80 > +#define DW_IC_ENABLE_STATUS 0x9c > +#define DW_IC_CLR_RESTART_DET 0xa8 > +#define DW_IC_SMBUS_INTR_STAT 0xc8 > +#define DW_IC_SMBUS_INTR_MASK 0xcc > +#define DW_IC_CLR_SMBUS_INTR 0xd4 > +#define DW_IC_COMP_PARAM_1 0xf4 > +#define DW_IC_COMP_VERSION 0xf8 > +#define DW_IC_COMP_TYPE 0xfc > + > +/* DW_IC_CON bits */ > +#define DW_IC_CON_MASTER BIT(0) > +#define DW_IC_CON_SPEED_STD (1 << 1) > +#define DW_IC_CON_SPEED_FAST (2 << 1) > +#define DW_IC_CON_SPEED_HIGH (3 << 1) > +#define DW_IC_CON_SPEED_MASK GENMASK(2, 1) > +#define DW_IC_CON_10BITADDR_SLAVE BIT(3) > +#define DW_IC_CON_10BITADDR_MASTER BIT(4) > +#define DW_IC_CON_RESTART_EN BIT(5) > +#define DW_IC_CON_SLAVE_DISABLE BIT(6) > +#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7) > +#define DW_IC_CON_TX_EMPTY_CTRL BIT(8) > +#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9) > +#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11) > + > +/* DW_IC_DATA_CMD bits */ > +#define DW_IC_DATA_CMD_DAT GENMASK(7, 0) > +#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11) > + > +/* DW_IC_INTR_* bits */ > +#define DW_IC_INTR_RX_UNDER BIT(0) > +#define DW_IC_INTR_RX_OVER BIT(1) > +#define DW_IC_INTR_RX_FULL BIT(2) > +#define DW_IC_INTR_TX_OVER BIT(3) > +#define DW_IC_INTR_TX_EMPTY BIT(4) > +#define DW_IC_INTR_RD_REQ BIT(5) > +#define DW_IC_INTR_TX_ABRT BIT(6) > +#define DW_IC_INTR_RX_DONE BIT(7) > +#define DW_IC_INTR_ACTIVITY BIT(8) > +#define DW_IC_INTR_STOP_DET BIT(9) > +#define DW_IC_INTR_START_DET BIT(10) > +#define DW_IC_INTR_GEN_CALL BIT(11) > +#define DW_IC_INTR_RESTART_DET BIT(12) > +#define DW_IC_INTR_MST_ON_HOLD BIT(13) > + > +/* DW_IC_ENABLE bits */ > +#define DW_IC_ENABLE_ENABLE BIT(0) > +#define DW_IC_ENABLE_ABORT BIT(1) > + > +/* DW_IC_STATUS bits */ > +#define DW_IC_STATUS_ACTIVITY BIT(0) > +#define DW_IC_STATUS_TFE BIT(2) > +#define DW_IC_STATUS_RFNE BIT(3) > +#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5) > +#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6) > +#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7) > + > +/* DW_IC_SMBUS_INTR_* bits */ > +#define DW_IC_SMBUS_INTR_ALERT BIT(10) > + > +#endif /* __LINUX_DESIGNWARE_I2C_H */ > -- > 2.50.1 >