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Sun, 6 Sep 2026 21:07:38 -0700 Date: Sun, 6 Sep 2026 21:07:35 -0700 From: Nicolin Chen To: "Kiryl Shutsemau (Meta)" CC: Will Deacon , Robin Murphy , "Joerg Roedel" , Jason Gunthorpe , "Pranjal Shrivastava" , Mostafa Saleh , "Thierry Reding" , Krishna Reddy , Jonathan Hunter , Breno Leitao , Kyle McMartin , Usama Arif , , , , , Subject: Re: [PATCH v4 1/2] iommu/arm-smmu-v3: Add a cmdq_entries module parameter Message-ID: References: <20260902121724.3494954-1-kas@kernel.org> <20260902121724.3494954-2-kas@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260902121724.3494954-2-kas@kernel.org> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|DS4PR12MB9611:EE_ X-MS-Office365-Filtering-Correlation-Id: b42698db-8e8f-4cc2-b686-08df0c959731 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|36860700016|7416014|1800799024|376014|10067099003|3023799007|22082099003|18002099003|56012099006|11063799006|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eOyYzVghoExKprLyE19S+5xwN5IP4cl6z0+YaHCoNCZFz5GH+VNR8dbJ9gyDroN/HlySKXOjulycXQdWEuKCsYEDXPqdhRUFt+2Cg1GePktU+AAsUr0fU3BHO149jnH0754CHfU7NjzuUMjyh0THUW5SV3jwY+GCCc8EiRY0H+BmzNsCiPS2qVB2+xYibGakKWXhIfdaJsT2KqLzNUZlbBIjxxSs2Hz5PAo+1SHmhlFKmJ+F8luC689PR4x1qC1LGBEkj9eUdr5OwZok8ItRLUGQ7QrAAHtEkIVA9i5zN/T0g/zG0ZHf++zQiJeM+l8Vy7R9KBeFgx1irvh23z1UYF6odDFOJfC0DcUtbP+zGu/Y4NOVsgLPxAwdymVOmEkYhDP3WXKszwgDlsv5riM57Y+7R/wMsiJzIia3VQYKTfjtDsxbxFzmwBXKU19E/Z0k X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2026 04:07:53.5565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b42698db-8e8f-4cc2-b686-08df0c959731 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9611 Hi, I think there can be some small cosmetic changes. I gave it a try, and it looks overall cleaner to me. Hope you would agree. On Wed, Sep 02, 2026 at 01:17:23PM +0100, Kiryl Shutsemau (Meta) wrote: > +/** > + * arm_smmu_queue_max_n_shift() - pick the log2 depth of a queue > + * @hw_shift: log2 depth the hardware allows, capped for natural alignment We can drop "capped for natural alignment" -- evtq/priq don't cap. > + * @ent_sz_shift: log2 of the queue entry size in bytes > + * @want: number of entries asked for, or zero to use @hw_shift Instead, rename to: @ceiling: default max_n_shift ceiling of the queue @ent_sz_shift: log2 of the queue entry size in bytes @new_ceiling: new ceiling to override; use the default if 0 > + * @want is rounded down to a power of two. It never sizes a queue below one > + * page, because coherent DMA is page granular: a shallower queue occupies the > + * same memory as one that fills the page, and arm_smmu_init_one_queue() stops > + * shrinking at a page too. > + */ > +static u32 arm_smmu_queue_max_n_shift(u32 hw_shift, u32 ent_sz_shift, u32 want) > +{ > + u32 page_shift = PAGE_SHIFT - ent_sz_shift; And let's call it "floor". It fits the comments and commit message. > + > + if (!want) > + return hw_shift; > + > + return min(hw_shift, max(ilog2(want), page_shift)); > +} > + > +/* > + * Command queues are also allocated by the Tegra241 CMDQV for its VCMDQs, which > + * need the same depth decision. > + */ > +u32 arm_smmu_cmdq_max_n_shift(u32 hw_shift) > +{ > + return arm_smmu_queue_max_n_shift(hw_shift, CMDQ_ENT_SZ_SHIFT, > + cmdq_entries); > +} Here, move in the natural alignment cap. u32 arm_smmu_cmdq_max_n_shift(u32 ceiling) { /* Capped to ensure natural alignment */ ceiling = min_t(u32, CMDQ_MAX_SZ_SHIFT, ceiling); return arm_smmu_queue_max_n_shift( ceiling, CMDQ_ENT_SZ_SHIFT, cmdq_max_entries ? ilog2(cmdq_max_entries) : 0); } > @@ -662,8 +663,8 @@ static int tegra241_vcmdq_alloc_smmu_cmdq(struct tegra241_vcmdq *vcmdq) > > /* Cap queue size to SMMU's IDR1.CMDQS and ensure natural alignment */ > regval = readl_relaxed(smmu->base + ARM_SMMU_IDR1); > - q->llq.max_n_shift = > - min_t(u32, CMDQ_MAX_SZ_SHIFT, FIELD_GET(IDR1_CMDQS, regval)); > + hw_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, FIELD_GET(IDR1_CMDQS, regval)); > + q->llq.max_n_shift = arm_smmu_cmdq_max_n_shift(hw_shift); Then, we can just use FIELD_GET() at the two call sites: smmu->cmdq.q.llq.max_n_shift = arm_smmu_cmdq_max_n_shift(FIELD_GET(IDR1_CMDQS, reg)); Thanks Nicolin