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On Wed, Aug 26, 2026 at 06:48:39PM +0100, Biju wrote: > From: Biju Das > > Add support for the MIPI DSI controller found on the Renesas RZ/G3L > (R9A08G046) SoC. The D-PHY global timing table of RZ/G3L SoC different > compared to the other SoCs. Introduce a dedicated D-PHY global timing > table rzg3l_mipi_dsi_global_timings and wire it up via a new > rzg3l_mipi_dsi_info hw_info variant for RZ/G3L SoC. > > Signed-off-by: Biju Das > --- > v1->v2: > * Moved set duty cycle to DU encoder. > v1->v2: > * Replaced syscon_field->pwrrdy in struct rzg3l_mipi_dsi_info. > --- > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 117 ++++++++++++++++++ > 1 file changed, 117 insertions(+) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 7df5f4a4161b..88ec0612d529 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -226,6 +226,107 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi_dsi_global_timings[] = { > }, > }; > > +static const struct rzg2l_mipi_dsi_timings rzg3l_mipi_dsi_global_timings[] = { > + { > + .hsfreq_max = 100000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 18, > + .tclk_zero = 35, > + .tclk_pre = 13, > + .tclk_post = 94, > + .tclk_trail = 10, > + .ths_zero = 16, > + .ths_trail = 22, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 150000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 16, > + .tclk_zero = 35, > + .tclk_pre = 13, > + .tclk_post = 94, > + .tclk_trail = 10, > + .ths_zero = 16, > + .ths_trail = 15, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 250000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 13, > + .tclk_zero = 35, > + .tclk_pre = 13, > + .tclk_post = 58, > + .tclk_trail = 8, > + .ths_zero = 16, > + .ths_trail = 10, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 400000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 12, > + .tclk_zero = 35, > + .tclk_pre = 4, > + .tclk_post = 58, > + .tclk_trail = 7, > + .ths_zero = 16, > + .ths_trail = 9, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 600000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 11, > + .tclk_zero = 35, > + .tclk_pre = 4, > + .tclk_post = 35, > + .tclk_trail = 5, > + .ths_zero = 16, > + .ths_trail = 6, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 1000000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 11, > + .tclk_zero = 35, > + .tclk_pre = 4, > + .tclk_post = 35, > + .tclk_trail = 5, > + .ths_zero = 16, > + .ths_trail = 6, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > + { > + .hsfreq_max = 1500000000, > + .t_init = 79801, > + .tclk_prepare = 10, > + .ths_prepare = 11, > + .tclk_zero = 35, > + .tclk_pre = 4, > + .tclk_post = 35, > + .tclk_trail = 4, > + .ths_zero = 16, > + .ths_trail = 5, > + .ths_exit = 15, > + .tlpx = 9, Ok > + }, > +}; This is aligned with: 9.5 MIPI DSI Interface (DSI) Table 9.5-4 (Recommended Setting Values of the DSI D-PHY Timing Register) Of the the RZ/G3L reference manual. > + > /** > * struct rzv2h_mipi_dsi_timings - Timing parameter table structure > * > @@ -1580,7 +1681,23 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info = { > .activation_dly = 1000, > }; > > +static const struct rzg2l_mipi_dsi_hw_info rzg3l_mipi_dsi_info = { > + .dphy_init = rzg2l_mipi_dsi_dphy_init, > + .dphy_exit = rzg2l_mipi_dsi_dphy_exit, > + .dphy_conf_clks = rzg2l_dphy_conf_clks, > + .dsi_global_timings = rzg3l_mipi_dsi_global_timings, > + .num_dsi_global_timings = ARRAY_SIZE(rzg3l_mipi_dsi_global_timings), > + .link_reg_offset = 0x10000, > + .dphyctrl0_init_val = DSIDPHYCTRL0_CMN_MASTER_EN | DSIDPHYCTRL0_EN_BGR, > + .min_dclk = 5440, > + .max_dclk = 187500, > + .activation_dly = 100, > + .features = RZ_MIPI_DSI_FEATURE_16BPP, > + .pwrrdy = true, > +}; > + > static const struct of_device_id rzg2l_mipi_dsi_of_table[] = { > + { .compatible = "renesas,r9a08g046-mipi-dsi", .data = &rzg3l_mipi_dsi_info, }, Looks good to me. Reviewed-by: Tommaso Merciai Kind regards, Tommaso > { .compatible = "renesas,r9a09g057-mipi-dsi", .data = &rzv2h_mipi_dsi_info, }, > { .compatible = "renesas,rzg2l-mipi-dsi", .data = &rzg2l_mipi_dsi_info, }, > { /* sentinel */ } > -- > 2.43.0 >