From: Thierry Reding <thierry.reding@kernel.org>
To: Linmao Li <lilinmao@kylinos.cn>
Cc: lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org,
robh@kernel.org, bhelgaas@google.com, jonathanh@nvidia.com,
mmaddireddy@nvidia.com, linux-tegra@vger.kernel.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: tegra264: Fix Link Capabilities register offset
Date: Thu, 27 Aug 2026 12:02:39 +0200 [thread overview]
Message-ID: <apAK-s-gl3moinqH@orome> (raw)
In-Reply-To: <20260827093919.2825467-1-lilinmao@kylinos.cn>
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On Thu, Aug 27, 2026 at 05:39:19PM +0800, Linmao Li wrote:
> The PCI Express Link Capabilities and Link Status registers are at offsets
> 0x0c and 0x12 from the capability header, respectively. Since the driver
> uses 0x5a for Link Status, Link Capabilities starts at 0x54, not 0x56.
>
> Reading a 16-bit value at 0x56 returns the upper half of the Link
> Capabilities register. When a hotplug-capable port has no link during
> probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> width from unrelated bits and requests the wrong interconnect bandwidth.
>
> Use the correct Link Capabilities offset.
>
> Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
> Signed-off-by: Linmao Li <lilinmao@kylinos.cn>
> ---
> drivers/pci/controller/pcie-tegra264.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Yes, that's what the manual says, too. /o\
Acked-by: Thierry Reding <treding@nvidia.com>
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next prev parent reply other threads:[~2026-08-27 10:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 9:39 Linmao Li
2026-08-27 10:02 ` Thierry Reding [this message]
2026-08-27 17:03 ` Bjorn Helgaas
2026-08-27 17:11 ` Thierry Reding
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