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Sat, 29 Aug 2026 11:22:10 -0700 Date: Sat, 29 Aug 2026 11:22:09 -0700 From: Nicolin Chen To: "Aneesh Kumar K.V (Arm)" CC: , , , , Alexey Kardashevskiy , Catalin Marinas , Dan Williams , "Jason Gunthorpe" , Joerg Roedel , Jonathan Cameron , Marc Zyngier , Pranjal Shrivastava , Robin Murphy , Samuel Ortiz , Steven Price , Suzuki K Poulose , Will Deacon , Xu Yilun Subject: Re: [RFC PATCH v4 01/16] iommu/arm-smmu-v3: Discover RME support and realm IRQ topology Message-ID: References: <20260427085344.941627-1-aneesh.kumar@kernel.org> <20260427085344.941627-2-aneesh.kumar@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260427085344.941627-2-aneesh.kumar@kernel.org> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|PH7PR12MB5711:EE_ X-MS-Office365-Filtering-Correlation-Id: c01f161a-66a5-42ff-3b63-08df05fa74a4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|1800799024|23010399003|7416014|376014|22082099003|18002099003|56012099006|11063799006|4143699003|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sCsc+0kxK69zsufTPcnVlAYvvv/Q80k/YYL+Q/epGYA5LcyO++w3wovt3qKfbQyUiJiz0s7ekCpNAYQUo7EjnD3xoBVC5MC4WRo/RTol/7rQMGFvunTTGzH6Ii+RqY2O6kyDDtv8KQXhfLmxV4uxGVcVAhva/zKV1PKf59WFAKuSAvyALq00wQkpxjuHSr5vNHSFybZxHLcpvGBQgqYKKQC8IMfE81cX0viI3AGwwjNlMzQ44SbV3m4Gtbz2TvRsyjYo1vLISlTP3NxDO7SCSBtiF0Qtev1uBQvC5z2AofIlXCrF/VO9gGYcTS2hqbfa4gCYl2JCyXSLj7RmT9QbLxoZayeLuXamO2oxteUEtMZzdcrXkUQvfgOj1+AaSYbEvd9BgwqTAJ8CNu93GDDoGpT1XOoRHi2Ln6ST2fFRBOuRChY6XCnrhXsor3uLVIB5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2026 18:22:16.4844 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c01f161a-66a5-42ff-3b63-08df05fa74a4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5711 On Mon, Apr 27, 2026 at 02:23:29PM +0530, Aneesh Kumar K.V (Arm) wrote: > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-realm.c > @@ -0,0 +1,124 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (C) 2026 ARM Ltd. > + */ > + > +#include > +#include > +#include > + > +#include "arm-smmu-v3.h" > + > +#define RMI_PSMMU_IRQ_GERROR BIT(0) > +#define RMI_PSMMU_IRQ_EVENTQ BIT(1) > +#define RMI_PSMMU_IRQ_PRIQ BIT(2) > +#define RMI_PSMMU_IRQ_CMDQ BIT(3) [...] > + if (irq == smmu->realm_evtq_irq) > + notify_flags = RMI_PSMMU_IRQ_EVENTQ; > + else if (irq == smmu->realm_gerr_irq) > + notify_flags = RMI_PSMMU_IRQ_GERROR; > + else if (irq == smmu->realm_pri_irq) > + notify_flags = RMI_PSMMU_IRQ_PRIQ; These are defined as BIT(x)... > + if (rmi_psmmu_irq_notify(smmu->base_phys, > + notify_flags, &event)) { [...] > + rmi_psmmu_event_consume(smmu->base_phys, notify_flags); .. and passed to RMI_PSMMU_IRQ_NOTIFY and RMI_PSMMU_EVENT_CONSUME. RMI_PSMMU_IRQ_NOTIFY takes RmiPsmmuIrqSet type, which is a 4-bit field that has a range of [BIT(0), BIT(3)]. So this is correct. However, RMI_PSMMU_EVENT_CONSUME takes RmiPsmmuIrq type, which is a 2-bit field that has a range of [0x0, 0x3]. So this seems wrong. > +void arm_smmu_setup_realm_irqs(struct arm_smmu_device *smmu) > +{ > + int irq, ret; > + > + irq = smmu->realm_evtq_irq; > + if (irq) { > + ret = devm_request_threaded_irq(smmu->dev, irq, NULL, > + arm_smmu_realm_notify_thread, > + IRQF_ONESHOT, > + "arm-smmu-v3-realm-evtq", > + smmu); These IRQ numbers are raw numbers forwarded by firmware and then returned by RMI_PSMMU_INFO: + if ((psmmu_info->flags & RMI_PSMMU_IRQCFG_MASK) == + RMI_PSMMU_IRQCFG_IRQ_WIRED) { + smmu->realm_gerr_irq = psmmu_info->gerror_intr_num; + smmu->realm_evtq_irq = psmmu_info->eventq_intr_num; + smmu->realm_pri_irq = psmmu_info->priq_intr_num; Should they be converted to Linux IRQ numbers before forwarded to devm_request_threaded_irq? > @@ -782,6 +787,9 @@ struct arm_smmu_device { > > int gerr_irq; > int combined_irq; > + int realm_gerr_irq; > + int realm_evtq_irq; > + int realm_pri_irq; Nit: this series adds a few realm-specific things in the top SMMU structure. Maybe a "struct arm_realm_psmmu" can make them clearer. Thanks Nicolin