From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CE4437A846; Thu, 3 Sep 2026 07:55:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788422121; cv=none; b=IY2at4Jr0vySp9hBjFng7Q4tSF3SbQcidqdGnATso8TzNBgpvpCYfSS2JXNbDWsMmIuTXdRMAIgiV2mtzoI50Gky9upgL86ZaYvSIQvw+40Q7zQ8RtT1iHVhJ+8CL20rdao8Dg+TNp7Ah8EzyKMtERkSnudB9g6xgT7Z0YokHLs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788422121; c=relaxed/simple; bh=oEZUz5rtQGFea8KnrSaezcDsHUvWAvb933VhFcmwdNo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=ot+1SMvD3eL5YBiCtUIyyg8cp1JFXs3+9HVvZUO7JVIhLKvZMgSdE66sb3H/t/8Xo22I/DWYusN0BMlwtvYkBTcGrRnfcjBpbMewbtspO8daAY0IDMf16YBKTrjGHLDLyUrIVN3SpMA8HoWXvjmV56HxAunxfNmms6m1sDJPiX0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GrkABiE+; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GrkABiE+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1788422120; x=1819958120; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=oEZUz5rtQGFea8KnrSaezcDsHUvWAvb933VhFcmwdNo=; b=GrkABiE+TCHGYonjuuxSizZFnu2+Kg7gP+InSAPOWhOlmlgaCDlN5hc+ QOsQWAJyX+Oly2oP1dsRGBNumC5UPLKoqgQQrB9OJFbZXbsuPmiod0Ieb hdou4c4C3etVdsNKLYf9ZbknBOZ0YCK0rdzpCgvc7jXMP7WbypRyMrN3C Hyud/EayhWemwJ5+GTxFRvba4vUDSPIktkXRfSlcbNXATu9j1Je/I2Z+q diJl91oghZZWVhtJRPaGMKF6eMrdg7IbD/mRbUYWP4H4mzqGQlH4iAToE Xf6eCb1mm1OF7ms/RsksSegc9B5qpNivaY4esmOif/DYsxgROreuN6wzt A==; X-CSE-ConnectionGUID: wHsreohsRKeyscnFBT3OnA== X-CSE-MsgGUID: 6Wz3crWYTr+2GIWd3zTDZQ== X-IronPort-AV: E=McAfee;i="6800,10657,11894"; a="88740325" X-IronPort-AV: E=Sophos;i="6.25,258,1779174000"; d="scan'208";a="88740325" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 00:55:20 -0700 X-CSE-ConnectionGUID: oyT5rocWS+SsY9hvb/0CoQ== X-CSE-MsgGUID: j4FQMz8rTmGyM8J7dZ0kKw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.25,258,1779174000"; d="scan'208";a="273400058" Received: from smoticic-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.28]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2026 00:55:17 -0700 Date: Thu, 3 Sep 2026 10:55:15 +0300 From: Andy Shevchenko To: Tsz Shan Chan Cc: Jonathan Cameron , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Andy Shevchenko , linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Tsz Shan Chan Subject: Re: [PATCH v3 2/5] iio: light: vcnl4000: clear DRDY interrupt when buffer disabled Message-ID: References: <20260903-vcnl4000-v3-0-5e69c2e715a8@jacques.com.au> <20260903-vcnl4000-v3-2-5e69c2e715a8@jacques.com.au> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260903-vcnl4000-v3-2-5e69c2e715a8@jacques.com.au> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Thu, Sep 03, 2026 at 02:53:47PM +1000, Tsz Shan Chan wrote: > on vcnl4010/4020, interrupt status bits are cleared by writing 1 to the > corresponding bit in the ISR register. If data ready interrupt triggers > when the iio buffer is disabled, the DRDY bit is never cleared and the > interrupt line stays low. > > Clear the DRDY bit in the interrupt handler when the buffer is disabled. Shouldn't this have a Fixes tag? -- With Best Regards, Andy Shevchenko