From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from hall.aurel32.net (hall.aurel32.net [195.154.119.183]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CE3A04F55C0; Thu, 3 Sep 2026 17:28:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.154.119.183 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788456494; cv=none; b=PLNiNnjwczsGudQ73mUsYm29i0135puTVYKSTE8WCZst90ivogMjUzTrXPbC4YpR1S+hGugSnyPQ1Ib6uT0ubaDpU+/jPdUs8pTjgnXlJlC472HgWVV1bo0/640KULBcoOwjELpBJgQ8XvZf9xArG83Q2Rxn3dvI7wqX0s/k6to= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1788456494; c=relaxed/simple; bh=UN2yFs+CjxLdNQHVvA2p/QDc/Ekfx3+H4B8JEjwMEcc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=DyEF03ekpoDNOECIFZ7+HQuJD0H65hibtlaUPrwbWJ+AKKEF0/JFHgs4WQ765ny749wwIVm+amZ7u9HdALD2EMCxlSWi9Gsu+vHQTvt8R7wpfLc1cphHPeSRxM248n+ZUVyyVkYorKKkgYajmVFrEoWzzcaKNymZsnQ8QuAvcvE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net; spf=pass smtp.mailfrom=aurel32.net; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b=kznrT9qY; arc=none smtp.client-ip=195.154.119.183 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=aurel32.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=aurel32.net Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=aurel32.net header.i=@aurel32.net header.b="kznrT9qY" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=aurel32.net ; s=202004.hall; h=In-Reply-To:Content-Type:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Content-Transfer-Encoding:From:Reply-To: Subject:Content-ID:Content-Description:X-Debbugs-Cc; bh=KkPABGwemNUQ0ip/GlWnS3cY+MjjrMjAD9CrZqkw+bI=; b=kznrT9qYaP2qBayj49vjRDtMgR TN3mC4zpISHFi68VgyysMrXTmbt7LMpWYemXhf6oVzpRx/qqQQBRIBexi6wkPJtxtxRde9Ragj6PB QQMfmhG4LTWlnXEYeqFP/S4wHxIWlSjcpV7x9SxWToDjIpfG+H5UELWPjdJrhHDxu1lBBPVK0QAkf q+c9EwTW2KM/KBrdOdpGUObysX+q0J+dODraSar+1b91CU7fsvQpHjA8eWnJqrCzXn7VEFZgdCws9 EmCScqVtIohYOzndBZwUgVrJeFfgWOONN3WfvQFVRHrgVkXfDSbU8hos2iXj7oYe/1DOQ5rrL1Td1 YEiLE95w==; Received: from authenticated user by hall.aurel32.net with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1x2BEB-0000000Fhdv-3dP3; Thu, 03 Sep 2026 19:27:55 +0200 Date: Thu, 3 Sep 2026 19:27:55 +0200 From: Aurelien Jarno To: Troy Mitchell Cc: Michael Turquette , Inochi Amaoto , Alex Elder , Haylen Chu , stable@vger.kernel.org, Stephen Boyd , Brian Masney , Jerome Brunet , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4] clk: spacemit: k3: add CPU PLL rate tables Message-ID: Mail-Followup-To: Troy Mitchell , Michael Turquette , Inochi Amaoto , Alex Elder , Haylen Chu , stable@vger.kernel.org, Stephen Boyd , Brian Masney , Jerome Brunet , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , linux-clk@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org References: <20260903-k3-pll5-pll8-1800mhz-v4-1-afafd9cb47d9@linux.spacemit.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260903-k3-pll5-pll8-1800mhz-v4-1-afafd9cb47d9@linux.spacemit.com> User-Agent: Mutt/2.4.1 (2026-07-04) Hi Troy, On 2026-09-03 11:06, Troy Mitchell wrote: > The K3 CPU PLL rate tables currently describe only one rate per PLL, > although the hardware supports a wider range. > > PLL3 and PLL4 support rates from 1.05 to 2.4 GHz, while PLL5 and PLL8 > support rates from 1.05 to 2 GHz. Populate the tables with every > supported rate in 50 MHz steps. > > Cc: stable@vger.kernel.org # 7.0+ > Signed-off-by: Troy Mitchell > --- > The corresponding U-Boot changes are available at: > > - Add the CPU PLL rate tables: > https://github.com/spacemit-com/uboot-2022.10/commit/787b5cf44c8dbc99db886d5522c0c9cd5a96ffd6 > - Correct the 1.10 GHz and 2.15 GHz table entries: > https://github.com/spacemit-com/uboot-2022.10/commit/16a775c20e9efb54ca55352215e76eb3f12e6cf0 > --- > Changes in v4: > - Expand the update to every supported PLL3, PLL4, PLL5 and PLL8 rate. > - Drop Aurelien Jarno's Reviewed-by and Tested-by trailers because the > patch scope has expanded. > - Add U-Boot references for the complete tables and corrected entries. > - Link to v3: https://patch.msgid.link/20260831-k3-pll5-pll8-1800mhz-v3-1-530ed0978615@linux.spacemit.com > > Changes in v3: > - Mark the change for stable kernels starting with v7.0. > - Add Aurelien Jarno's Reviewed-by and Tested-by trailers. > - Rebase onto v7.3-rc1. > - Link to v2: https://patch.msgid.link/20260810-k3-pll5-pll8-1800mhz-v2-1-aabff510a797@linux.spacemit.com > > Changes in v2: > - Drop "clk: spacemit: re-enable PLLs after init"; the PLL init issue > will be handled in a separate series. > - Send the K3 PLL5 and PLL8 1.8 GHz rate-table update as a standalone > patch. > - Clarify that 1.8 GHz is nominal and 2 GHz is an overclocking rate. > - Link to v1: https://patch.msgid.link/20260804-k3-pll5-pll8-1800mhz-v1-0-a3a75866ce32@linux.spacemit.com > > To: Stephen Boyd > To: Brian Masney > To: Jerome Brunet > To: Yixun Lan > To: Paul Walmsley > To: Palmer Dabbelt > To: Albert Ou > To: Alexandre Ghiti > Cc: linux-clk@vger.kernel.org > Cc: linux-riscv@lists.infradead.org > Cc: spacemit@lists.linux.dev > Cc: linux-kernel@vger.kernel.org > --- > drivers/clk/spacemit/ccu-k3.c | 96 +++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) Thanks for the patch, it makes sense to add all the values, to support future firmware changes. The values match the ones in the vendor kernel. > diff --git a/drivers/clk/spacemit/ccu-k3.c b/drivers/clk/spacemit/ccu-k3.c > index 92b930d5ff30..950bf531c734 100644 > --- a/drivers/clk/spacemit/ccu-k3.c > +++ b/drivers/clk/spacemit/ccu-k3.c > @@ -29,15 +29,91 @@ static const struct ccu_pll_rate_tbl pll2_rate_tbl[] = { > CCU_PLLA_RATE(3000000000UL, 0x0b3e2000, 0x00000000, 0xa0558c8c), > }; > > +/* Keep the firmware default as the first entry. */ > static const struct ccu_pll_rate_tbl pll3_rate_tbl[] = { > + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), Is it really necessary to put this entry first? I guess it's the current default frequency, but we have seen it can evolve. From my tests, the driver seems to just keep the value configured by the firmware independently from the table order, so I am not sure it's necessary. > + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080), > + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181), > + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181), > + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282), > + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282), > + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282), > + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383), > + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383), > + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383), > + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484), > + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484), > + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484), > + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585), > + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585), > + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585), > + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686), > + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686), > + CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686), > + CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787), > + CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787), > CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), > + CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888), > + CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888), > + CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888), > + CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989), > }; > > +/* Keep the firmware default as the first entry. */ > static const struct ccu_pll_rate_tbl pll4_rate_tbl[] = { > + CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), > + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080), > + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181), > + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181), > + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282), > + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282), > + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282), > + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383), > + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383), > + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383), > + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484), > + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484), > + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484), > + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585), > + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585), > + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585), > + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686), > + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686), > + CCU_PLLA_RATE(2050000000UL, 0x0b2a2d55, 0x00005500, 0xa0558686), > + CCU_PLLA_RATE(2100000000UL, 0x0b2b3000, 0x00000000, 0xa0558787), > + CCU_PLLA_RATE(2150000000UL, 0x0b2c32aa, 0x0000ab00, 0xa0558787), > CCU_PLLA_RATE(2200000000UL, 0x0b2d3555, 0x00005500, 0xa0558787), > + CCU_PLLA_RATE(2250000000UL, 0x0b2e3800, 0x00000000, 0xa0558888), > + CCU_PLLA_RATE(2300000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0558888), > + CCU_PLLA_RATE(2350000000UL, 0x0b303d55, 0x00005500, 0xa0558888), > + CCU_PLLA_RATE(2400000000UL, 0x0b320000, 0x00000000, 0xa0558989), > }; > > +/* Keep the firmware default as the first entry. */ > static const struct ccu_pll_rate_tbl pll5_rate_tbl[] = { > + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585), Ditto > + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080), > + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181), > + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181), > + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282), > + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282), > + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282), > + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383), > + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383), > + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383), > + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484), > + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484), > + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484), > + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585), > + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585), > + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686), > + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686), > CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), > }; > > @@ -49,7 +125,27 @@ static const struct ccu_pll_rate_tbl pll7_rate_tbl[] = { > CCU_PLLA_RATE(2800000000UL, 0x0b3a1555, 0x00005500, 0xa0558b8b), > }; > > +/* Keep the firmware default as the first entry. */ > static const struct ccu_pll_rate_tbl pll8_rate_tbl[] = { > + CCU_PLLA_RATE(1800000000UL, 0x0b4b0000, 0x00000000, 0xa0458585), > + CCU_PLLA_RATE(1050000000UL, 0x0b2b3000, 0x00000000, 0xa0458080), > + CCU_PLLA_RATE(1100000000UL, 0x0b2d3555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1150000000UL, 0x0b2f3aaa, 0x0000ab00, 0xa0458181), > + CCU_PLLA_RATE(1200000000UL, 0x0b320000, 0x00000000, 0xa0458181), > + CCU_PLLA_RATE(1250000000UL, 0x0b340555, 0x00005500, 0xa0458181), > + CCU_PLLA_RATE(1300000000UL, 0x0b360aaa, 0x0000ab00, 0xa0458282), > + CCU_PLLA_RATE(1350000000UL, 0x0b381000, 0x00000000, 0xa0458282), > + CCU_PLLA_RATE(1400000000UL, 0x0b3a1555, 0x00005500, 0xa0458282), > + CCU_PLLA_RATE(1450000000UL, 0x0b3c1aaa, 0x0000ab00, 0xa0458383), > + CCU_PLLA_RATE(1500000000UL, 0x0b3e2000, 0x00000000, 0xa0458383), > + CCU_PLLA_RATE(1550000000UL, 0x0b402555, 0x00005500, 0xa0458383), > + CCU_PLLA_RATE(1600000000UL, 0x0b422aaa, 0x0000ab00, 0xa0458484), > + CCU_PLLA_RATE(1650000000UL, 0x0b443000, 0x00000000, 0xa0458484), > + CCU_PLLA_RATE(1700000000UL, 0x0b463555, 0x00005500, 0xa0458484), > + CCU_PLLA_RATE(1750000000UL, 0x0b483aaa, 0x0000ab00, 0xa0458585), > + CCU_PLLA_RATE(1850000000UL, 0x0b4d0555, 0x00005500, 0xa0458585), > + CCU_PLLA_RATE(1900000000UL, 0x0b4f0aaa, 0x0000ab00, 0xa0458686), > + CCU_PLLA_RATE(1950000000UL, 0x0b511000, 0x00000000, 0xa0458686), > CCU_PLLA_RATE(2000000000UL, 0x0b292aaa, 0x0000ab00, 0xa0558686), > }; I have tested the patch, and I confirm it fixes the boot hang with newer firmware, and will fix it if the default firmware values change again. My comments are just minor ones, so: Reviewed-by: Aurelien Jarno Tested-by: Aurelien Jarno Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net