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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339b123731sm39776875eec.18.2026.09.09.01.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 01:31:14 -0700 (PDT) Date: Wed, 9 Sep 2026 16:31:08 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/3] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Message-ID: References: <20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com> <20260907-nords_dprx-v1-2-d472af3f01b1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260907-nords_dprx-v1-2-d472af3f01b1@oss.qualcomm.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDA5NCBTYWx0ZWRfX6GplkUA+4o8w ZoAnuQQfrgdAO+pwo92w5TV1U7FLcCJH9pyuH2doC4YdtfV8KGq+RfFzv2yFL3vm6nc4iuBlk0Z 4DPqnI4r/zLVmWSDmpTuycjFqZAfsvU= X-Proofpoint-ORIG-GUID: rFZOwb9Vr0LNDEKwDRySePaUN8va1KzJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDA5NCBTYWx0ZWRfX4v35SIZUaZY6 RaH/NdoeANB56dzp7vOVOZpMIyiMacZFxXdL0l5q5hqVU5jkBTRD/bGP9xPmw4gwCuHou70/QJf cTd6OG06ZF+2hwnpy+QNlVxnQQqxsEvYClqmbT8LFT/GFeRTuW7qkGsEYMctIRCJ9LjRSH/p/cx fpgyYL8WTtbt3vsc72vLYcBaW7UYi5SjC6SSNXZOYxH9zIJ4RqhlOXEmhbCDRQ+WRgqh3BwYaxs 2ZjkSi/szTeHL08eP6vWOPdT2xbApWpZBpkEd+q1/rDWPT3QME9bD1KjC/oBUYU0+j9ss+MAoZc 3L4Qv3FjcNvlMH2lwbowlIWW+QmBX432DAzpzC4Q3z7WHF61Xovg5LnqYZaeHQttJB+L3nGKTJi PEtnlFRNo31DS5NapbsDzIGER8hD/cnYtFld39Yt7ZGT+oFYmNdQfUVWivaPxMHvWMbIewCGzL+ MoEWTtKtVwYX3mchrwg== X-Authority-Analysis: v=2.4 cv=Xey5Co55 c=1 sm=1 tr=0 ts=6aa11954 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=FJ8gEVljA5m4mNThiM4A:9 a=CjuIK1q_8ugA:10 a=bFCP_H2QrGi7Okbo017w:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: rFZOwb9Vr0LNDEKwDRySePaUN8va1KzJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090094 On Mon, Sep 07, 2026 at 01:56:14PM +0530, Taniya Das wrote: > Add bindings documentation for the Nord DisplayPort Receiver (DPRX) Clock Controller. > > Signed-off-by: Taniya Das > --- > .../bindings/clock/qcom,nord-dprxcc.yaml | 68 ++++++++++++++++++++++ > include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 +++++++++ > 2 files changed, 95 insertions(+) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..fbaaad1f3db3ff67589d6201ed0e25710c044614 > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,nord-dprxcc.yaml > @@ -0,0 +1,68 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,nord-dprxcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm DPRX Clock & Reset Controller on Nord > + > +maintainers: > + - Taniya Das > + > +description: | " |" can be dropped? > + Qualcomm dprx clock control module provides the clocks, resets and power > + domains on Nord. I'm not sure it provides power domains, as the driver registers no GDSCs and the binding has no #power-domain-cells. Shawn > + > + See also: > + include/dt-bindings/clock/qcom,nord-dprxcc.h > + > +properties: > + compatible: > + enum: > + - qcom,nord-dprxcc0 > + - qcom,nord-dprxcc1 > + > + clocks: > + items: > + - description: XO clock source > + - description: DPRX CFG AHB clock from NWGCC > + - description: Sleep clock source > + > + power-domains: > + description: > + MMCX power domain. > + maxItems: 1 > + > + required-opps: > + description: > + MMCX performance point. > + maxItems: 1 > + > +required: > + - compatible > + - clocks > + - power-domains > + - required-opps > + > +allOf: > + - $ref: qcom,gcc.yaml# > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + clock-controller@a940000 { > + compatible = "qcom,nord-dprxcc0"; > + reg = <0x0a940000 0xc000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&nwgcc NW_GCC_DPRX0_CFG_AHB_CLK>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > +... > diff --git a/include/dt-bindings/clock/qcom,nord-dprxcc.h b/include/dt-bindings/clock/qcom,nord-dprxcc.h > new file mode 100644 > index 0000000000000000000000000000000000000000..62c26b58ebef04f05ea1dc77664c03aaad65baa4 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,nord-dprxcc.h > @@ -0,0 +1,27 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H > +#define _DT_BINDINGS_CLK_QCOM_DPRX_CC_NORD_H > + > +/* DPRX_CC clocks */ > +#define DPRX_CC_AHB_CLK 0 > +#define DPRX_CC_AUD_CLK 1 > +#define DPRX_CC_AUDIO_CLK_SRC 2 > +#define DPRX_CC_CORE_AHB_DIV_CLK_SRC 3 > +#define DPRX_CC_CORE_AUD_DIV_CLK_SRC 4 > +#define DPRX_CC_CORE_RCG0_CLK_SRC 5 > +#define DPRX_CC_CORE_RCG2_CLK_SRC 6 > +#define DPRX_CC_CORE_RCG3_CLK_SRC 7 > +#define DPRX_CC_MDP_MEM_CLK 8 > +#define DPRX_CC_MMCX_XO_CLK 9 > +#define DPRX_CC_PLL0 10 > +#define DPRX_CC_PLL1 11 > +#define DPRX_CC_VID_MEM_CLK 12 > + > +/* DPRX_CC resets */ > +#define DPRX_CC_DPRX_BLK_BCR 0 > + > +#endif > > -- > 2.34.1 > >