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> > static cpumask_var_t amu_fie_cpus; > > > > +/* > > + * Switching the active PE on an NVIDIA Olympus SMT core can keep the core in > > + * two-thread active mode, with resources partitioned between the PEs. > > + * > > + * Prefer PE0 so PE1 can remain idle and the core can stay in full-resource > > + * mode. Firmware does not currently describe this preference, so detect > > + * Olympus by MIDR until a firmware interface is available. > > + */ > > Fix the firmware? > > If we add this MIDR kludge, I guarantee that it will never be fixed. Understood. The existing PPTT already describes the SMT relationship, but as far as I can tell ACPI doesn't currently provide a way to describe a preferred SMT sibling. Both PEs also have equal isolated performance, so representing this using different _CPC highest_perf values wouldn't accurately describe their capacity. I'll drop the MIDR-based enablement and coordinate with the firmware team on a proper ABI. In the meantime, for systems with the existing firmware, would an explicit kernel boot option be acceptable as a fallback? It'd enable SD_ASYM_PACKING at the SMT level and prefer the primary PE, but only when requested by the user; the kernel would not infer this policy from the CPU model. Other ideas? Thanks, -Andrea