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Wed, 9 Sep 2026 12:05:39 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46 via Frontend Transport; Wed, 9 Sep 2026 12:05:36 -0700 Date: Wed, 9 Sep 2026 12:05:34 -0700 From: Nicolin Chen To: Jonathan Cameron CC: Jason Gunthorpe , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 08/13] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Message-ID: References: <0b5282c7e850f1a1c650e43670899b4ef5335efd.1788222486.git.nicolinc@nvidia.com> <178846311318.1308030.4956293524348641228.b4-review@b4> <20260904141525.GT4157646@nvidia.com> <20260909105954.00002181@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260909105954.00002181@oss.qualcomm.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PEPF00000097:EE_|CY8PR12MB7489:EE_ X-MS-Office365-Filtering-Correlation-Id: 81bf4bde-d7d1-4319-7146-08df0ea56734 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|7416014|82310400026|36860700016|4143699003|5023799004|11063799006|56012099006|10067099003|6133799003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hgCvy1NpL6ihxvQiZDvdrp+yBMb18Ig9hUMxovZ7dT2rRwhKD70Z2dxklz3dNtRu87kic794EQMiEp2rG70KHyzyzhzqClJu3DBCQLM7ektZiE5Bz2NDqNjCtfKTP6k70J+nndiuxyI+XgL6nowKt+YO3S4DoG6HIlsfoztlE6/2Xvg8OktvkyniWQ0/IdRuRgN8MPjtDapVS6rmHQOs6yqt3TtIbG8cL2IU167eD9YgUv0n9GbnA62fIL0WeflEO4WEhbv/YIFz2SmIm/+WPDVUWeJt1b9lz/PdndkOzNZ9EzSo3mTufLp7/q9vNmDwaQlhbdWE4fuXLBF7IOFKkLpfbuoM+6ex0CMsufBSVsv9I18aJ/cFe2+79gzDb0UTynEZA+avgPkqA4L/wDIm8/EsCHH3YNVw/lt7yaMIzeU5uC6KlckmUusajXzRSCBl X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Sep 2026 19:06:07.1919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 81bf4bde-d7d1-4319-7146-08df0ea56734 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF00000097.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7489 On Wed, Sep 09, 2026 at 10:59:54AM -0700, Jonathan Cameron wrote: > On Fri, 4 Sep 2026 11:15:25 -0300 > Jason Gunthorpe wrote: > > > On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > > > arm_smmu_setup_irqs() has three failure paths that leave the priq without > > > > a handler: a missing priq IRQ line, devm_request_threaded_irq() failure on > > > > the priq IRQ, and devm_request_threaded_irq() failure on the combined IRQ. > > > > Each path warned but kept ARM_SMMU_FEAT_PRI set in smmu->features. > > > > > > > > With FEAT_PRI still set, arm_smmu_setup_irqs() enables IRQ_CTRL_PRIQ_IRQEN > > > > against a handler that does not exist, and a later change would then have > > > > arm_smmu_probe_device() call pci_enable_pri() on PCIe endpoints, allowing > > > > them to issue PRI Page Requests that pile up in the priq with no drainer. > > > > Separately, arm_smmu_device_reset() has already enabled CR0_PRIQEN before > > > > it invoked arm_smmu_setup_irqs(), so the hardware queue would stay enabled > > > > regardless of what setup_irqs decides. > > > > > > > > Clear ARM_SMMU_FEAT_PRI in all three failure paths, so that subsequent code > > > > treats PRI as unavailable. And disable CR0_PRIQEN after the setup function > > > > returns. > > > > > > > > A kdump kernel cannot service page requests: strip FEAT_PRI when detecting > > > > features, so downstream PRI setup is skipped. > > > > > > Dumb question - why can't a kdump kernel service page requests? > > > I'm nowhere near familiar enough with that stuff and I suspect I'm not > > > the only one who might be in that state and reading this series. > > > Configuration choice, or a fundamental thing? > > > > The initial issue is the streams are left in whatever state the crash > > kernel had them in, so it can be generating a bunch of PRIs with no > > place to put them. > > > > Though eventually we may find a device where dropping them is not good > > and they need to be NAK'd promptly.. > > > > But I think the real motivation here is to save memory in the kdump > > kernel.. > > Got it, so design decision rather than fundamental. Maybe tweak that text > to say > "A kdump kernel doesn't service page request" ? Sure. Fixed. Thanks Nicolin