From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Conor Dooley <conor@kernel.org>,
Jonathan Cameron <jic23@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, zhangfei.gao@oss.qualcomm.com
Subject: Re: [PATCH 1/2] dt-bindings: cache: qcom,llcc: Add Nord compatible
Date: Fri, 11 Sep 2026 14:31:37 +0800 [thread overview]
Message-ID: <aqOgSe_Q4YWBLnBJ@QCOM-aGQu4IUr3Y> (raw)
In-Reply-To: <20260910-nord_llcc-v1-1-30fd1cca65fe@oss.qualcomm.com>
On Thu, Sep 10, 2026 at 06:30:43PM +0530, Anurag Pateriya wrote:
> Nord has four DDR slices with four MACH9 LLCC banks each, so it exposes
> sixteen bank regions plus the shared broadcast OR/AND pair. Add its
> compatible with a matching reg/reg-names group and raise the top level
> maxItems to eighteen.
>
> Signed-off-by: Anurag Pateriya <anurag.pateriya@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-11 6:31 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-10 13:00 [PATCH 0/2] nord : llcc : Adding LLCC dt bindings and SCT configurations Anurag Pateriya
2026-09-10 13:00 ` [PATCH 1/2] dt-bindings: cache: qcom,llcc: Add Nord compatible Anurag Pateriya
2026-09-11 6:31 ` Shawn Guo [this message]
2026-09-11 13:04 ` Komal Bajaj
2026-09-10 13:00 ` [PATCH 2/2] soc: qcom: llcc: Add LLCC configuration for Nord Anurag Pateriya
2026-09-10 13:50 ` Zhangfei Gao
2026-09-11 6:38 ` Shawn Guo
2026-09-11 7:51 ` Abel Vesa
2026-09-11 13:06 ` Komal Bajaj
2026-09-22 10:21 ` Konrad Dybcio
2026-09-25 14:15 ` (subset) [PATCH 0/2] nord : llcc : Adding LLCC dt bindings and SCT configurations Bjorn Andersson
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