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From: Vinod Koul <vkoul@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	Kathiravan T <quic_kathirav@quicinc.com>,
	Baruch Siach <baruch@tkos.co.il>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>,
	Manu Gautam <mgautam@codeaurora.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 0/3] phy: qcom-qusb2: sort out register layouts
Date: Sun, 13 Sep 2026 11:52:14 +0530	[thread overview]
Message-ID: <aqZBFvKu24Ed_IKj@parshuram> (raw)
In-Reply-To: <20260706-fix-qusb2-v2-0-8d9cd73b1db7@oss.qualcomm.com>

On 06-07-26, 16:53, Dmitry Baryshkov wrote:
> IPQ6018 and MSM8996 use the same register layout, however for historical
> reasons ipq6018_regs_layout ended up correctly definig TEST1 register at
> 0x98 (because platforms using that layout didn't use autoresume), while
> msm8996_regs_layout used TEST_CTRL offset (0xb8) for the TEST1 layout
> entry. Fix handling of the autoresume register and definitions of those
> regs layouts.

This fails to apply on the current code, can you please rebase

-- 
~Vinod

      parent reply	other threads:[~2026-09-13  6:22 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 13:53 Dmitry Baryshkov
2026-07-06 13:53 ` [PATCH v2 1/3] phy: qcom-qusb2: enable autoresume on Talos platforms Dmitry Baryshkov
2026-07-06 15:37   ` Konrad Dybcio
2026-07-06 13:53 ` [PATCH v2 2/3] phy: qcom-qusb2: correst PHY description for IPQ6018 Dmitry Baryshkov
2026-07-07  7:39   ` Konrad Dybcio
2026-07-06 13:53 ` [PATCH v2 3/3] phy: qcom-qusb2: describe autoresume bit Dmitry Baryshkov
2026-07-07  8:43 ` [PATCH v2 0/3] phy: qcom-qusb2: sort out register layouts Konrad Dybcio
2026-09-09 16:17 ` Manivannan Sadhasivam
2026-09-13  6:22 ` Vinod Koul [this message]

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