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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33ba4e9b359sm23888008eec.14.2026.09.13.23.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Sep 2026 23:27:23 -0700 (PDT) Date: Sun, 13 Sep 2026 23:27:21 -0700 From: Qiang Yu To: Bjorn Helgaas Cc: Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Konrad Dybcio , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] PCI: qcom: Block accesses to downstream devices on link down Message-ID: References: <20260911171807.GA402207@bhelgaas> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260911171807.GA402207@bhelgaas> X-Proofpoint-GUID: dc0K2DK4LgBatF5QbQ9DYWJEqnlmRk-2 X-Authority-Analysis: v=2.4 cv=Pv4G/AM3 c=1 sm=1 tr=0 ts=6aa793cd cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=mQlHuAPmx7t5lgBK5VUA:9 a=CjuIK1q_8ugA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE0MDA4OSBTYWx0ZWRfX5Y+UhJw1Rg92 zkPWduxNNBsf+wn9qablSP0BsmsMkFotN3WJH8YOf6/SsEnTSq2AfHTBIZP9jIUKpGYEGWKXVir N9DDjpMYWgOPzU1eTYHkXKSVwUlRmAM= X-Proofpoint-ORIG-GUID: dc0K2DK4LgBatF5QbQ9DYWJEqnlmRk-2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE0MDA4OSBTYWx0ZWRfXzaZug1kZ/3iz EZcys+JVacRD9jW7Ryd9OBDkpnonKo4YWd6PJi1B1x7fa11hYaW3eUAA76DAGYyts9Yw08idl14 jk2m3g7HrV/FFoQLVc8psXd8T4zj6PM5xpc1ZXRjcEfn0ocvFMGDdNpOu8UgVkAtgOUg9r1YpfX ynQgxinlwhyOvR6vLKsvurrpkxiMro3FrQG5Gid5bLzW/wM8TIzN9BYbOFZ06dPbLeZ+tMnCuB+ ODK11rtRI5JYIcWjpuDMZngofKzdZcPVUP+uUfIbijFerQci2pjzZP1qF8IleyhDOcqV2XAc6Vo UktcZ5dwubpPRbMM3+uka4G/WtbbpSD5HUSGsL5TRFkRe/t8VJKgEv0y1/plrrxMMOPn3rnYWK4 6DIGm7J2nODGGtVoCGjAyimt4EoTjH883SN6l9W8suw2nDrv4xkCPfZIt/dHYbvL1gPJVdpF/iM Rh/VMMibEt8C+KuZ97w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-14_02,2026-09-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 adultscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609140089 On Fri, Sep 11, 2026 at 12:18:07PM -0500, Bjorn Helgaas wrote: > On Fri, Sep 11, 2026 at 08:17:29AM +0200, Manivannan Sadhasivam wrote: > > On Tue, Sep 08, 2026 at 06:00:30PM -0500, Bjorn Helgaas wrote: > > > On Wed, Aug 19, 2026 at 11:36:54PM -0700, Qiang Yu wrote: > > > > After a PCIe link goes down, software may still access the BAR > > > > (MMIO) space or configuration space of devices behind that link > > > > before recovery has run. As the link is down, these accesses > > > > never complete, resulting in a storm of Completion Timeout AERs. > > > > > > What is special about qcom here? It seems like the Completion > > > Timeouts and AER interrupts should happen with every PCIe > > > controller. > > > > The special behavior which is common across many (not all) ARM SoCs > > is that they don't synthesize all-one response for completion > > timeouts, unlike RCs in x86 machines. Rather, they return AXI error > > response, resulting in CPU treating them as SError, in-addition to > > AER storm. > > > > Commit message missed mentioning SError though. > > I don't know how SError works, but this sounds like a pretty big open > issue with respect to RAS. I don't think we want a kernel panic > because a device failed to respond to a config or MMIO access, e.g., > if a card or Thunderbolt cable got unplugged. > > > > Is this mitigating an issue that will still happen on other > > > controllers and should be solved elsewhere, e.g., by changing the > > > software that accesses the BAR to look for the error responses it > > > gets when the Completion Timeout happens? > > > > That would be too late as we don't get a proper error response. > > That's why this patch is used. > > > > > The patch refers to the ECAM blocker (which I assume affects > > > config accesses) and doesn't mention MMIO. Is the SLV_AXI stuff > > > for MMIO? > > > > ECAM blocker is a Qcom's custom implementation which prevents the > > config access to go out of the link and terminate the request > > properly. And yes, it doesn't affect MMIO like BAR. > > The commit log implies that the patch blocks both config and MMIO > accesses: "software may access MMIO or config space ... Use ECAM > blocker to drop these accesses." If the ECAM blocker only affects > config accesses, we need to reword that description. > This patch can block both config space and MMIO accesses. > If this patch doesn't affect MMIO accesses, I assume they will still > fail and lead to SError? I'm a little dubious about the utility of > this because I assume most runtime driver accesses will be to MMIO > space, not config space. > > I assume this is also racy: any config access that happens in the > window between the link going down and the ECAM blocker being enabled > will still fail and result in SError, right? > Yes, there is a window between link going down and the ECAM blocker being enabled, this is why I mentioned this patch can *reduce* the completion timeout errors in commit msg. - Qiang Yu > > > Assume the root port leads to a switch, and the switch has two > > > links to downstream devices. If one of the switch downstream > > > links goes down, is this going to kill the device on the other > > > link that is still up? > > > > ECAM blocker is only enabled when the PCIe link to the Root Port > > goes down. We don't get LDn interrupt when the switch downstream > > link goes down. In that case, the switch should synthesize the error > > response if the CPU tries to access the unavailable device. > > For config or MMIO reads targeting a device below a switch, if the > link to the device is down, I think the switch will return an > Unsupported Request completion without data (PCIe r7.0, sec 2.3.1.1). > > The PCIe spec doesn't prescribe whether RC synthesizes data to > complete the read, but x86 RCs typically synthesize ~0 data. I guess > some arm64 RCs assert SError instead of completing the read. > > IIUC, if the link from the RP goes down, we'll take the LDn interrupt, > enable ECAM blocker, and future config reads would return ~0. But if > a link below a switch goes down, there's no LDn interrupt and it > sounds like future config reads would result in a UR Cpl and SError.