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X-CSE-ConnectionGUID: lnn62VZWTRSmHi+VtrqtDg== X-CSE-MsgGUID: NMmViMFURRyVNgg3bEA2Iw== X-IronPort-AV: E=McAfee;i="6800,10657,11904"; a="89930525" X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="89930525" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa108.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2026 01:12:16 -0700 X-CSE-ConnectionGUID: Pk3tLVsuSq+B8gP2yd78ag== X-CSE-MsgGUID: j+X708W/Q1mtQ7SjumjlBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,102,1787036400"; d="scan'208";a="269292406" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.245.29]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2026 01:12:11 -0700 Date: Mon, 14 Sep 2026 11:12:09 +0300 From: Andy Shevchenko To: Nuno =?iso-8859-1?Q?S=E1?= Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org, linux-sound@vger.kernel.org, linux-spi@vger.kernel.org, Vinod Koul , Frank Li , Lars-Peter Clausen , Eugeniy Paltsev , =?iso-8859-1?Q?Am=E9lie?= Delaunay , Maxime Coquelin , Alexandre Torgue , Jonathan Cameron , David Lechner , Andy Shevchenko , Jaroslav Kysela , Takashi Iwai , Mark Brown , Frank Li Subject: Re: [PATCH v4 08/10] ALSA: pcm_dmaengine: Use dma_slave_caps bus width helpers Message-ID: References: <20260911-dmaengine-support-wider-dma-masks-v4-0-72b8fd4cc78e@analog.com> <20260911-dmaengine-support-wider-dma-masks-v4-8-72b8fd4cc78e@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260911-dmaengine-support-wider-dma-masks-v4-8-72b8fd4cc78e@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Fri, Sep 11, 2026 at 06:25:43PM +0100, Nuno Sá wrote: > Use the dma_slave_caps bus width helpers instead of reading the legacy > src_addr_widths and dst_addr_widths masks directly. > > Keep the existing default assumption of 1, 2 and 4 byte widths when the > DMA channel does not report slave capabilities. ... > int snd_dmaengine_pcm_refine_runtime_hwparams( > struct snd_pcm_hardware *hw, > struct dma_chan *chan) > { > + enum dma_slave_buswidth default_widths[] = { > + DMA_SLAVE_BUSWIDTH_1_BYTE, > + DMA_SLAVE_BUSWIDTH_2_BYTES, > + DMA_SLAVE_BUSWIDTH_4_BYTES, > + }; > struct dma_slave_caps dma_caps; > - u32 addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); > + dma_buswidth_mask_t bus_widths = {}; Do you really need the zeroing? > snd_pcm_format_t i; > int ret = 0; > if (!hw || !chan || !dma_data) > return -EINVAL; > > + ret = dma_bus_width_set_many(bus_widths, default_widths, > + ARRAY_SIZE(default_widths)); > + if (ret) > + return ret; I assume that if ret == 0, bus_widths should be set accordingly. -- With Best Regards, Andy Shevchenko