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X-CSE-ConnectionGUID: u61zRsqXTMOj7MBabWAKEQ== X-CSE-MsgGUID: 4d5eij4uTt6PeLVwnI1HWQ== X-IronPort-AV: E=McAfee;i="6800,10657,11905"; a="100967378" X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="100967378" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 00:32:02 -0700 X-CSE-ConnectionGUID: gcNLgQiYRZKOETkK+/DZpA== X-CSE-MsgGUID: rfWMtsATQle5Hq81vExF3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,103,1787036400"; d="scan'208";a="269199181" Received: from smoticic-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.203]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2026 00:31:57 -0700 Date: Tue, 15 Sep 2026 10:31:55 +0300 From: Andy Shevchenko To: Nuno =?iso-8859-1?Q?S=E1?= Cc: linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-iio@vger.kernel.org, linux-sound@vger.kernel.org, linux-spi@vger.kernel.org, Vinod Koul , Frank Li , Lars-Peter Clausen , Eugeniy Paltsev , =?iso-8859-1?Q?Am=E9lie?= Delaunay , Maxime Coquelin , Alexandre Torgue , Jonathan Cameron , David Lechner , Andy Shevchenko , Jaroslav Kysela , Takashi Iwai , Mark Brown , Frank Li Subject: Re: [PATCH v4 08/10] ALSA: pcm_dmaengine: Use dma_slave_caps bus width helpers Message-ID: References: <20260911-dmaengine-support-wider-dma-masks-v4-0-72b8fd4cc78e@analog.com> <20260911-dmaengine-support-wider-dma-masks-v4-8-72b8fd4cc78e@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Sep 14, 2026 at 04:39:38PM +0100, Nuno Sá wrote: > On Mon, Sep 14, 2026 at 11:12:09AM +0300, Andy Shevchenko wrote: > > On Fri, Sep 11, 2026 at 06:25:43PM +0100, Nuno Sá wrote: ... > > > int snd_dmaengine_pcm_refine_runtime_hwparams( > > > struct snd_pcm_hardware *hw, > > > struct dma_chan *chan) > > > { > > > + enum dma_slave_buswidth default_widths[] = { > > > + DMA_SLAVE_BUSWIDTH_1_BYTE, > > > + DMA_SLAVE_BUSWIDTH_2_BYTES, > > > + DMA_SLAVE_BUSWIDTH_4_BYTES, > > > + }; > > > struct dma_slave_caps dma_caps; > > > - u32 addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | > > > - BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | > > > - BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); > > > > > + dma_buswidth_mask_t bus_widths = {}; > > > > Do you really need the zeroing? > > I think so. dma_bus_width_set_many() just does __set_bit() under the > hood so if we do not zero initialize I think we could be left with some > random bits in the mask. Unless I'm missing something. Hmm... Since it's a recipient, I would expect it will be filled correctly independently on the garbage it might have had initially. So, perhaps call a bitmap_zero() with the maximum size in there? > > > snd_pcm_format_t i; > > > int ret = 0; > > > > > if (!hw || !chan || !dma_data) > > > return -EINVAL; > > > > > > + ret = dma_bus_width_set_many(bus_widths, default_widths, > > > + ARRAY_SIZE(default_widths)); > > > + if (ret) > > > + return ret; > > > > I assume that if ret == 0, bus_widths should be set accordingly. As mentioned here, if no error, bus_widths should be fine to use.) -- With Best Regards, Andy Shevchenko