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From: Peng Fan <peng.fan@oss.nxp.com>
To: Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	Marc Zyngier <maz@kernel.org>, Oliver Upton <oupton@kernel.org>,
	Fuad Tabba <fuad.tabba@linux.dev>,
	Joey Gouly <joey.gouly@arm.com>,
	Steffen Eiden <seiden@linux.ibm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>
Cc: "Ivan T. Ivanov" <iivanov@suse.de>,
	Francesco Dolcini <francesco@dolcini.it>,
	Frank Li <frank.li@nxp.com>,
	linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
	linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
	imx@lists.linux.dev, Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH v4] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue
Date: Tue, 15 Sep 2026 23:02:54 +0800	[thread overview]
Message-ID: <aqleHm4stDi3Pt//@shlinux89> (raw)
In-Reply-To: <20260824-imx8qm-cache-coherency-v4-v4-1-b2e528c7d05e@nxp.com>

Hi All,

On Mon, Aug 24, 2026 at 12:02:04PM +0800, Peng Fan (OSS) wrote:
>From: Peng Fan <peng.fan@nxp.com>
>
>According to NXP errata document IMX8_1N94W[1], the i.MX8QuadMax SoC
>suffers from a cache coherency issue (ERR050104). The upper bits, above
>bit 35, of the ARADDR and ACADDR buses within the Arm A53 subsystem
>have been incorrectly connected. This causes some TLBI and IC
>maintenance operations exchanged between the A53 and A72 core clusters
>to be corrupted.
>

Any comments?

Thanks,
Peng

      parent reply	other threads:[~2026-09-15 14:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-24  4:02 Peng Fan (OSS)
2026-08-25  7:06 ` Franz Schnyder
2026-09-15 15:04   ` Peng Fan
2026-09-15 15:02 ` Peng Fan [this message]

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