From: Frank Li <Frank.li@oss.nxp.com>
To: "Peng Fan (OSS)" <peng.fan@oss.nxp.com>
Cc: Frank Li <Frank.Li@nxp.com>, Vinod Koul <vkoul@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Frank Li <Frank.Li@kernel.org>,
imx@lists.linux.dev, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Peng Fan <peng.fan@nxp.com>
Subject: Re: [PATCH 1/2] dt-bindings: dma: fsl,edma: add iommu-map property
Date: Wed, 16 Sep 2026 11:46:05 -0500 [thread overview]
Message-ID: <aqrHzWp7joSs593p@SMW015318> (raw)
In-Reply-To: <20260916-edma-iommu-v1-1-e1731968081e@nxp.com>
On Wed, Sep 16, 2026 at 11:55:25PM +0800, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@nxp.com>
>
> Add the iommu-map property to the fsl,edma binding to allow per-channel
> IOMMU stream ID mapping. This enables IOMMU translation for individual
> eDMA channels, where paired channels can share the same stream ID and
> channels without an entry operate in bypass mode.
>
> Also add a new example using fsl,imx95-edma5 that demonstrates the
> iommu-map usage with per-channel mappings.
>
> Assisted-by: Claude:claude-opus-4-6
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
> .../devicetree/bindings/dma/fsl,edma.yaml | 89 ++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> index f609038e35ae1..cb8c650a5bb90 100644
> --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
> @@ -104,6 +104,15 @@ properties:
> Bit semantics: 0 means channel available, 1 means channel unavailable
> default: 0
>
> + iommu-map:
> + description:
> + Maps DMA channel numbers to IOMMU stream IDs. Each entry maps one
> + or more channels to a contiguous range of stream IDs. Paired channels
> + may share the same stream ID. Channels without an entry operate in
> + bypass mode.
> + minItems: 1
> + maxItems: 64
> +
> required:
> - "#dma-cells"
> - compatible
> @@ -351,3 +360,83 @@ examples:
> <&pd IMX_SC_R_DMA_3_CH6>,
> <&pd IMX_SC_R_DMA_3_CH7>;
> };
> +
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + dma-controller@42000000 {
> + compatible = "fsl,imx95-edma5";
> + reg = <0x42000000 0x210000>;
> + #dma-cells = <3>;
> + dma-channels = <64>;
> + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk 0>;
> + clock-names = "dma";
> + /*
> + * Per-channel IOMMU mapping. Each channel
> + * occupies one entry; paired channels share
> + * the same SID. Channels without an entry
> + * operate in bypass mode.
> + */
> + iommu-map = <2 &smmu 0x30 1>,
> + <3 &smmu 0x30 1>,
> + <4 &smmu 0x31 1>,
> + <5 &smmu 0x31 1>,
> + <6 &smmu 0x32 1>,
> + <7 &smmu 0x32 1>,
> + <8 &smmu 0x33 1>,
> + <9 &smmu 0x33 1>,
> + <10 &smmu 0x34 1>,
> + <11 &smmu 0x34 1>,
> + <12 &smmu 0x35 1>,
> + <13 &smmu 0x35 1>,
> + <14 &smmu 0x36 1>,
> + <15 &smmu 0x36 1>,
> + <16 &smmu 0x37 1>,
> + <17 &smmu 0x37 1>,
> + <18 &smmu 0x38 1>,
> + <19 &smmu 0x38 1>;
> + };
>
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-09-16 16:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-16 15:55 [PATCH 0/2] dmaengine: fsl-edma: add per-channel IOMMU support Peng Fan (OSS)
2026-09-16 15:55 ` [PATCH 1/2] dt-bindings: dma: fsl,edma: add iommu-map property Peng Fan (OSS)
2026-09-16 16:46 ` Frank Li [this message]
2026-09-16 15:55 ` [PATCH 2/2] dmaengine: fsl-edma: add per-channel IOMMU support via iommu-map Peng Fan (OSS)
2026-09-16 18:23 ` Frank Li
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