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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33bf5af4f0bsm13392763eec.24.2026.09.16.20.46.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2026 20:46:42 -0700 (PDT) Date: Thu, 17 Sep 2026 11:46:36 +0800 From: Shawn Guo To: Bartosz Golaszewski Cc: Shawn Guo , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Rob Herring , Krzysztof Kozlowski , Conor Dooley , brgl@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] arm64: dts: qcom: nord: add GPI DMA controller nodes Message-ID: References: <20260916-nord-gpi-dts-v1-0-073e3f9c19d0@oss.qualcomm.com> <20260916-nord-gpi-dts-v1-1-073e3f9c19d0@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260916-nord-gpi-dts-v1-1-073e3f9c19d0@oss.qualcomm.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTE3MDA0NCBTYWx0ZWRfX3k4OX9Bfw+pb PHyOTfYb3MBZshoafLKofrtQTeGSBgJ4sG7LKK2WakAsa/bs3C1nkMrAv1e7X3LOqQCHzfVzyBH hPO4q90NLfZOuZORTmGTcJvgFH6TWcs= X-Proofpoint-GUID: wyZfFAdlW9iR1Qai7ufe7x0XUQjmWIN3 X-Authority-Analysis: v=2.4 cv=N4m8hG9B c=1 sm=1 tr=0 ts=6aab62a4 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=RWIZ5eiTQN5k4lw2HGAA:9 a=CjuIK1q_8ugA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: wyZfFAdlW9iR1Qai7ufe7x0XUQjmWIN3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTE3MDA0NCBTYWx0ZWRfXwcTFPGzaM50R p5kbp/4OEQ94B+6ta1vxY9BFDiyIG1xfFZ9yQbZZJ4ZNbzFJH0meuEKcLWnRfKFW+jOmDjvBlAf d/OhzlF7FrvhrdbyjguK0DMTyXMa/LHSUFEyirpLocT9Kp9ttF/ddXw3MspHBEBdsfhref6l0Lv V0CJE24ZCTA46GSIV1Uiq9dYif0vSRsc8RyrRUE32RSx7vrWi46uqKVUt4vmHzuauvtr1Bbteha Tm6WVfh5NaKr1HoeBa2SVVEIKtLaY54aGssWX5CJFBQhrOtvriIemY9wDEW17Xf0BGKY0lwlFar +JbVkMxEY8knGJSInNdPiXp2YpTeW72Q5rumuuH1/2wRbzbTteg2bglA1GpFVIPd87X/C7SNYWh 2U0QPflX2C32LhkhH2F7ID2BYPypMbbFUogKUxRDsuCqZTR0UHGZ4Iqe/RVGIbNbXOLd5VYnH6m kGtU2+jAPn59jlq4F3g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-16_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 adultscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609170044 On Wed, Sep 16, 2026 at 05:55:38PM +0200, Bartosz Golaszewski wrote: > Add GPI DMA controller nodes for all three QUPv3 engines. > > Signed-off-by: Bartosz Golaszewski > --- > arch/arm64/boot/dts/qcom/nord.dtsi | 67 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 67 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi > index 22c026c32fb5..870033a106db 100644 > --- a/arch/arm64/boot/dts/qcom/nord.dtsi > +++ b/arch/arm64/boot/dts/qcom/nord.dtsi > @@ -3,6 +3,7 @@ > * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > */ > > +#include Nit: this include should probably go with patch 2/2? Or could these two patches be squashed? Shawn > #include > #include > #include > @@ -1062,6 +1063,28 @@ soc: soc@0 { > dma-ranges = <0 0 0 0 0x10 0>; > ranges = <0 0 0 0 0x10 0>; > > + gpi_dma2: dma-controller@800000 { > + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x00800000 0x0 0x60000>; > + #dma-cells = <3>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <12>; > + dma-channel-mask = <0xfff>; > + iommus = <&apps_smmu_0 0x15b6 0x0>; > + status = "disabled"; > + }; > + > qupv3_2: geniqup@8c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x008c0000 0x0 0x2000>; > @@ -1260,6 +1283,28 @@ uart20: serial@898000 { > }; > }; > > + gpi_dma0: dma-controller@900000 { > + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x00900000 0x0 0x60000>; > + #dma-cells = <3>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <12>; > + dma-channel-mask = <0xfff>; > + iommus = <&apps_smmu_2 0x1016 0x0>; > + status = "disabled"; > + }; > + > qupv3_0: geniqup@9c0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x009c0000 0x0 0x2000>; > @@ -1431,6 +1476,28 @@ uart5: serial@994000 { > }; > }; > > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0x0 0x00a00000 0x0 0x60000>; > + #dma-cells = <3>; > + interrupts = , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + , > + ; > + dma-channels = <12>; > + dma-channel-mask = <0xfff>; > + iommus = <&apps_smmu_2 0x1056 0x0>; > + status = "disabled"; > + }; > + > qupv3_1: geniqup@ac0000 { > compatible = "qcom,geni-se-qup"; > reg = <0x0 0x00ac0000 0x0 0x2000>; > > -- > 2.47.3 > >