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Zhou (OSS)" Cc: Laurent Pinchart , Frank Li , Mauro Carvalho Chehab , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Loic Poulain , "linux-media@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" Subject: Re: [PATCH v4 07/11] media: imx8-isi: Select MSB-aligned RAW input from pixel link on i.MX95 Message-ID: References: <20260929-isi_imx952-v4-0-e69f89c7c651@oss.nxp.com> <20260929-isi_imx952-v4-7-e69f89c7c651@oss.nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: PH8PR22CA0005.namprd22.prod.outlook.com (2603:10b6:510:2d1::18) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|AMDPR04MB11650:EE_ X-MS-Office365-Filtering-Correlation-Id: bbd8da86-1827-4566-9083-08df1f0d7e46 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|19092799006|7416014|23010399003|4143699003|11063799006|10067099003|3023799007|56012099006|18002099003|22082099003; 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Zhou (OSS) wrote: > Hi Frank, > > Thanks for your review. > > > NXP Confidential Please remove this tags before send ... > > > + */ > > > +static bool isi_raw_in_msb(const struct mxc_isi_plat_data *pdata) { > > > + return pdata->model == MXC_ISI_IMX95; > > > > Can you add bool in plat_data to avoid check model? In case future other chip > > also use msb and complex check logic here. > > I used the model field here to be consistent with the approach suggested by Laurent > during the v2 review. > > In v2, I used a Boolean(bool raw_out_lsb) in plat_data to determine whether the ISI RAW > output should be LSB-aligned, and Laurent suggested using the model field instead. Based > on that feedback, I followed the same approach here for the RAW input alignment. > > Please see the discussion here for more details: > https://lore.kernel.org/all/20260915000520.GB2804748@killaraus.ideasonboard.com/ Laurent base on single SoC. But most likely it is not true in future. Use model field is not extentable enough. Now can't prefer use mode at most subsystem. I can reply original thread. Frank > > Best Regards > G.N Zhou > > > > > Frank > > > > > +} > > > + > > > static void mxc_isi_channel_set_control(struct mxc_isi_pipe *pipe, > > > enum mxc_isi_input_id input, > > > unsigned int vc, > > > @@ -357,6 +373,10 @@ static void mxc_isi_channel_set_control(struct > > mxc_isi_pipe *pipe, > > > val |= CHNL_CTRL_VC_ID_1(vc >> 2); > > > } > > > > > > + /* Select MSB-aligned RAW data from the Pixel Link when needed. */ > > > + if (isi_raw_in_msb(pipe->isi->pdata)) > > > + val |= CHNL_CTRL_RAW_IN_MSB_ALIGN; > > > + > > > mxc_isi_write(pipe, CHNL_CTRL, val); > > > > > > mutex_unlock(&pipe->lock); > > > diff --git a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > > > b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > > > index 5f66b7c9cd1c..35438abf3172 100644 > > > --- a/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > > > +++ b/drivers/media/platform/nxp/imx8-isi/imx8-isi-regs.h > > > @@ -20,6 +20,7 @@ > > > #define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 0 > > > #define CHNL_CTRL_CHAIN_BUF_2_CHAIN 1 > > > #define CHNL_CTRL_SW_RST BIT(24) > > > +#define CHNL_CTRL_RAW_IN_MSB_ALIGN > > BIT(22) /* i.MX{91,93,95} */ > > > /* > > > * CHNL_CTRL_BLANK_PXL: i.MX8{QM,QXP} only > > > * CHNL_CTRL_VC_ID_1, CHNL_CTRL_VC_ID_1_MASK: i.MX95 only > > > > > > -- > > > 2.34.1 > > > > > >