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Wed, 30 Sep 2026 13:03:27 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 13:03:25 -0700 Date: Wed, 30 Sep 2026 13:03:23 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , , Thomas Gleixner , Radu Rendec , Bjorn Helgaas , , , "Greg Kroah-Hartman" , , "Danilo Krummrich" , Subject: Re: [PATCH v11 12/16] iommu/tegra241-cmdqv: Add a helper to quiesce VCMDQs Message-ID: References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-13-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF00022BCC:EE_|SA1PR12MB9515:EE_ X-MS-Office365-Filtering-Correlation-Id: 4aa70a6c-6335-4843-fbde-08df1f2df82a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700016|7416014|23010399003|1800799024|10067099003|4143699003|18002099003|22082099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TBXQaHaBS/RnquBLYm/Sb9Lvj5DYwBpR4k1nVHr8OdF6EQorX/Swd/8n7EH4ngo6BdgtXIho3v+KQ8ofoYKq0pbwxJ+jRCgMssLhdbA6vpVnEi01xQ0TJ9gr03uLK+bGO810o8G66ofPWFLc+lc6TCryJVF27yO5SyFBQJ4LSFz2Uc//mTr2r6kNd2RwYL+2CA0pEFEHXQrYS4ShME7MRQ5x6Bt9IYHNoz03r552SHqP7CKvoSLQyi+xQxeHlVxVumKV+5CMyx3fLlZwnCm/23iij1/5EuqeScC8Ml+P0ektVAMpdZeUSCWxUsj7SXV15dFX+O4idi3qkX1R2A9OK0zq2FqsIHO/VP2ygRPZPiNky8q3nTpdotCH+LR7P6pO+hmA16d6R/MIrh1oqjp2gAtcsePo02ZHKTBDmNZgpdWEsftnQzOxiDhrFwxtbDYw X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 20:04:00.5393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4aa70a6c-6335-4843-fbde-08df1f2df82a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF00022BCC.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9515 On Wed, Sep 30, 2026 at 07:57:12PM +0000, Pranjal Shrivastava wrote: > I'm planning to add an impl->suspend op now.. that will cover this, and > also the late breaking IRQ changes you're referring to in the other > thread. Roughly: > - set STOP_FLAG on all lvcmdqs > - wait for owners & drain all lvcmdqs > - handle any pending CMDQV errors > - tegra241_vintf_hw_deinit(vintf0) > > I'll call it from arm_smmu_runtime_suspend() before gating the main > CMDQ, so the CMD_SYNC in tegra241_vcmdq_hw_flush_timeout() still goes > through and any late cmd simply falls back to smmu->cmdq. That sounds good to me. Nicolin