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Wed, 30 Sep 2026 13:34:02 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 13:34:00 -0700 Date: Wed, 30 Sep 2026 13:33:58 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , , Thomas Gleixner , Radu Rendec , Bjorn Helgaas , , , "Greg Kroah-Hartman" , , "Danilo Krummrich" , Subject: Re: [PATCH v11 11/16] iommu/arm-smmu-v3: Add CMDQ_PROD_STOP_FLAG to gate CMDQ submissions Message-ID: References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-12-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260929034510.2023173-12-praan@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992B:EE_|IA0PR12MB8088:EE_ X-MS-Office365-Filtering-Correlation-Id: 86b60a45-7e8a-45bc-4108-08df1f323978 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|1800799024|36860700016|376014|7416014|10067099003|56012099006|4143699003|6133799003|3023799007|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: xZ76xcwU+inpz4G/xHQdo3USWplLCsPcxXY1+azViTidbEqkQQ+IKMsSzZTyqeJymdMuGOnxAbkEKmVsqdD1L8p9R2hab/4jlCJ6jgDCYZj8tajz6Rzqnxv059pEWSCvhI9lMYDdUU8JPqtD+YLdI/UF3joS4ajf7kvpfTDnQ0Omfu+lENykwzHYl35pmoGvl79v0ckeUdmycH8GViRX/YUUS3mC2yZIMVdteYnoajaI9dx+/qPmTranraaPejqsOXMsVZAVZU5+ReuNKfNWV/0FNtlHKeOPRa83471Z9xy9C72tnni6fSVSQBOf48iAY2ei5nAyFue+deiyMtne3ttNIZSwkYd/FUh1tCQ9Cm8R3hVpZo4nXMvmvb828PIfF33PQ8cC7qnQdGu8Sw/8/mKm02hWVEW+NT8su4vOggtL4l9ioWreiuxr8UwX1Gaz X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 20:34:28.1127 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86b60a45-7e8a-45bc-4108-08df1f323978 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8088 On Tue, Sep 29, 2026 at 03:45:05AM +0000, Pranjal Shrivastava wrote: > @@ -726,13 +727,42 @@ int __arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, > do { > u64 old; > > + /* > + * If the SMMU is suspended/suspending, any new CMDs are elided. > + * This loop is the Point of Commitment. If we haven't cmpxchg'd > + * our new indices yet, we can safely bail. Once the indices are > + * committed, we MUST write valid commands to those slots to > + * avoid indefinite polling in the drain function. > + */ > + if (Q_STOP(llq.prod)) { > + local_irq_restore(flags); > + return 0; > + } Sashiko pointed out this: " Can this early return cause memory corruption by silently dropping ATC invalidations? When the SMMU suspends, Q_STOP(llq.prod) becomes true. If a driver or background thread then calls dma_unmap() to free a buffer while a PCIe endpoint (with ATS enabled) is suspended to a state like D0, the SMMU driver will observe the stop flag here in __arm_smmu_cmdq_issue_cmdlist(). By bailing out and returning 0 (success) without actually submitting the CMDQ_OP_ATC_INV command to the hardware, the IOMMU core is misled into freeing the memory while the PCIe endpoint's Address Translation Cache (ATC) retains the stale translation. When the PCI device resumes, or if it issues a TLP while in D0, it could use the stale ATC entry to access the now-freed memory, bypassing IOMMU protections. Are we assuming endpoint drivers clear their own ATC or that a hardware reset handles it? Client endpoint drivers typically lack an API to manually clear the ATC, and SMMU hardware resets do not broadcast ATC invalidations to endpoints. " We may get away from the TLB maintenance. But ATC can be the case broken by the stop flag? Nicolin