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Wed, 30 Sep 2026 14:44:33 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 14:44:31 -0700 Date: Wed, 30 Sep 2026 14:44:28 -0700 From: Nicolin Chen To: Suravee Suthikulpanit CC: , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v6 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Message-ID: References: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> <20260930092344.5616-5-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260930092344.5616-5-suravee.suthikulpanit@amd.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231A:EE_|PH7PR12MB8055:EE_ X-MS-Office365-Filtering-Correlation-Id: 62566f1b-c983-49a9-a16f-08df1f3c0e71 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|23010399003|36860700016|7416014|82310400026|1800799024|10067099003|4143699003|6133799003|56012099006|18002099003|11063799006|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gTqu2xJ/VjGI1H+e+/CVz/1TCJGCEFOk0QQtEYVH+1jzMGi8B3mSgP4iRJwl+ZAMsX7gl4zLTipSnSScm62bg+lk49plZEbAOUXCIudF6TebT+In07VUWW0VhkSMQaaiLpSJlDlr/Z+vA45RilFB0WUiNrx5V6cBft/GAIy5KEb2YqW2Fr/zfVkuG0ZurWMRGGjYsRDe8+uc2AObh4YNQyZhklQFN/8pVu8ZMfXa8WU/iyvV+jtduUX0XZIXDP7KsRhWGHDBtNq22AvU9CyKJ0oAd9AcL3jVa84izHrvJoXihSRBg1Roo/SMeBjmjAR31Vwg3jPdxcyPJxx6BgWtKMoBGOSglDi3RHuzOdHkC55b7pIRxitHPutAnlbd7Hl5XqZXCTiwne8n70HLOXomBHKFOI+Te57VF2WoE+q/iRCzr0FXrNpDtOvafiOnnVL6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 21:44:51.0501 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62566f1b-c983-49a9-a16f-08df1f3c0e71 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231A.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8055 On Wed, Sep 30, 2026 at 09:23:24AM +0000, Suravee Suthikulpanit wrote: > Introduce a new enum iommu_viommu_type (IOMMU_VIOMMU_TYPE_AMD) for AMD > vIOMMU along with the struct iommu_viommu_amd, which is used to initialize > IOMMUFD vIOMMU instance when calling struct iommu_ops.viommu_init(). > > Also, hook up struct iomufd_viomu_ops.alloc_domain_nested to connect > nested domain allocation with AMD vIOMMU implementation. > > Only report a non-zero viommu size when the type is AMD and > amd_iommu_viommu_enabled() is true for the device's IOMMU. > > Additional initialization will be added in subsequent patches. > > Reviewed-by: Jason Gunthorpe > Signed-off-by: Suravee Suthikulpanit Reviewed-by: Nicolin Chen