From: Andi Shyti <andi.shyti@kernel.org>
To: Helen Koike <koike@igalia.com>
Cc: rodrigo.vivi@intel.com, demarchi@kernel.org,
intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
tvrtko.ursulin@igalia.com, linux-kernel@vger.kernel.org,
kernel-dev@igalia.com
Subject: Re: [PATCH v2] drm/xe/lrc: Restore CTX_CS_INDIRECT_CTX_OFFSET programming for ADL
Date: Thu, 1 Oct 2026 10:45:17 +0200 [thread overview]
Message-ID: <ar3_LjzklapoN1tM@zenone.zhora.eu> (raw)
In-Reply-To: <20260930170434.317671-1-koike@igalia.com>
Hi Helen,
On Wed, Sep 30, 2026 at 02:04:30PM -0300, Helen Koike wrote:
> CTX_CS_INDIRECT_CTX_OFFSET default value is not retrieved from the GPU
> by inhibit+context save mechanism since it is not part of the Engine
> Context. Thus, at restore, 0x0 is programed back to the GPU, which is
/programed/programmed/
> an invalid value according to the PRM.
...
> /*
> * Enable INDIRECT_CTX leaving INDIRECT_CTX_OFFSET at its default: it
> - * varies per engine class, but the default is good enough
> + * varies per engine class, but the default is good enough, except on
> + * Alder Lake.
> */
> xe_lrc_write_ctx_reg(lrc,
> CTX_CS_INDIRECT_CTX,
> (xe_bo_ggtt_addr(lrc->bo) + state.offset) |
> /* Size in CLs. */
> (state.written * sizeof(u32) / 64));
> + if (GRAPHICS_VER(lrc_to_xe(lrc)) < 20)
Are you assuming that only Alder Lake is xe < 20?
As you are restoring the original code for render and compute,
would it make sense also add a check for class being
XE_EGINE_CLASS_RENDER || XE_ENGINE_CLASS_COMPUTE?
Andi
> + xe_lrc_write_ctx_reg(lrc,
> + CTX_CS_INDIRECT_CTX_OFFSET,
> + CTX_INDIRECT_CTX_OFFSET_DEFAULT);
>
> return 0;
> }
> --
> 2.54.0
>
next prev parent reply other threads:[~2026-10-01 8:45 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 17:04 Helen Koike
2026-09-30 23:29 ` Matt Roper
2026-10-01 14:17 ` Helen Koike
2026-10-01 8:45 ` Andi Shyti [this message]
2026-10-01 18:00 ` Helen Koike
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