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From: Will Deacon <will@kernel.org>
To: Leo Yan <leo.yan@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Mike Leach <mike.leach@arm.com>,
	James Clark <james.clark@linaro.org>,
	Anshuman Khandual <anshuman.khandual@arm.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Tamas Petz <tamas.petz@arm.com>,
	Tamas Zsoldos <tamas.zsoldos@arm.com>,
	Michiel van Tol <michiel.vantol@arm.com>,
	Dev Jain <dev.jain@arm.com>, David Hildenbrand <david@kernel.org>,
	Yabin Cui <yabinc@google.com>, James Morse <james.morse@arm.com>,
	coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 2/2] perf: arm_spe: Prefer large AUX mappings
Date: Thu, 1 Oct 2026 08:16:09 +0100	[thread overview]
Message-ID: <ar4Iuanz_vA4twGP@willie-the-truck> (raw)
In-Reply-To: <20260930164311.GK14479@e132581.arm.com>

On Wed, Sep 30, 2026 at 05:43:11PM +0100, Leo Yan wrote:
> On Mon, Aug 10, 2026 at 04:10:48PM +0100, Will Deacon wrote:
> > On Mon, Aug 10, 2026 at 03:44:42PM +0100, Leo Yan wrote:
> > > Commit 18049c8cff9c ("perf/aux: Allocate non-contiguous AUX pages by
> > > default") made the AUX allocator use order-0 pages by default unless a
> > > PMU explicitly asks for contiguous allocations.
> > 
> > But that commit specifically calls out SPE as benefitting from
> > non-contiguous pages:
> > 
> >   "For instance, ARM SPE and TRBE operate with virtual pages, and
> >    Coresight ETR allocates a separate buffer. For these PMUs,
> >    allocating contiguous AUX pages unnecessarily exacerbates memory
> >    fragmentation. This fragmentation can prevent their use on
> >    long-running devices."
> > 
> > so why doesn't passing PERF_PMU_CAP_AUX_PREFER_LARGE reintroduce the
> > problems that 18049c8cff9c was trying to solve?
> 
> How about adding a field to struct pmu to specify a preferred maximum
> page order for the AUX buffer? The perf core could try that order first
> and fall back to smaller orders if the allocation fails.

I'm not sure that's thr right place for it, really. The driver has no
clue about whether it makes sense to use large contiguous mappings or
not, so I'd have thought that decision should be driven from userspace
(e.g. like MADV_HUGEPAGE) because it really depends on the user's
preference and isn't a fixed property of the hardware.

> For example, the Neoverse V2 TRM documents:
> 
>   L1 Trace Buffer Extension (TRBE) TLB: 1 entry

Wow, they really pulled out the stops for that implementation. I bet
we're supposed to be grateful for that entry!

> Given the single L1 TRBE TLB entry, the TRBE driver could prefer
> PMD_ORDER (2 MiB with 4 KiB pages) to reduce TLB pressure. This reflects
> the hardware characteristic.
> 
> This could be a trade-off instead of using PERF_PMU_CAP_AUX_PREFER_LARGE,
> avoiding large contiguous allocations that could reintroduce the Android
> OOM issue. I did a quick test with this approach and the results look
> positive.

I really don't want the driver to second-guess userspace based on whatever
information it happens to have hard-coded about the specific CPU it's
running on.

Will

      reply	other threads:[~2026-10-01  7:16 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-10 14:44 [PATCH 0/2] perf/arm: Prefer large AUX mappings for CoreSight and SPE Leo Yan
2026-08-10 14:44 ` [PATCH 1/2] coresight: perf: Prefer large AUX mappings Leo Yan
2026-08-10 14:44 ` [PATCH 2/2] perf: arm_spe: " Leo Yan
2026-08-10 15:10   ` Will Deacon
2026-08-10 17:41     ` Leo Yan
2026-08-11  9:02       ` James Clark
2026-08-11 10:17         ` Leo Yan
2026-09-01 17:06           ` Leo Yan
2026-09-30 16:43     ` Leo Yan
2026-10-01  7:16       ` Will Deacon [this message]

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