From: Beata Michalska <beata.michalska@arm.com>
To: Vladimir Murzin <vladimir.murzin@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com,
will@kernel.org, suzuki.poulose@arm.com, James.Morse@arm.com,
xuewen.yan94@gmail.com, seanwang1@lenovo.com,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap
Date: Thu, 1 Oct 2026 10:50:44 +0200 [thread overview]
Message-ID: <ar4e5A5tytSaTWg5@arm.com> (raw)
In-Reply-To: <0dc8a173-2d8f-4a05-9624-6d95c2fdb622@arm.com>
On Wed, Sep 30, 2026 at 10:21:28AM +0100, Vladimir Murzin wrote:
> Hi Beata,
Hi Vladimir,
>
> On 9/29/26 16:42, Beata Michalska wrote:
> > Move the workaround from the erratum 2457168-specific cpucap to a generic
> > broken AMU constant-counter one. This keeps the existing Cortex-A510
> > handling unchanged while allowing other errata with similar AMU constant
> > counter issue to share the capability bit and call sites.
> >
> > Cc: <stable@vger.kernel.org>
> > Signed-off-by: Beata Michalska <beata.michalska@arm.com>
> > ---
> > arch/arm64/Kconfig | 8 ++++++++
> > arch/arm64/kernel/cpu_errata.c | 23 +++++++++++++++++------
> > arch/arm64/kernel/cpufeature.c | 2 +-
> > arch/arm64/kernel/topology.c | 7 ++++---
> > arch/arm64/tools/cpucaps | 2 +-
> > 5 files changed, 31 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> > index b5a51b0ef9440..3b6c052d46a18 100644
> > --- a/arch/arm64/Kconfig
> > +++ b/arch/arm64/Kconfig
> > @@ -1040,9 +1040,17 @@ config ARM64_ERRATUM_1902691
> >
> > If unsure, say Y.
> >
> > +config ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
> > + bool
> > + # Targeting errata affecting AMEVCNTR01, the AMU constant counter.
> > + # On affected CPUs the counter may not increment at the expected rate,
> > + # making it unreliable. As a result, AMU users should treat it as
> > + # unavailable rather than relying on misleading counter values.
> > +
> > config ARM64_ERRATUM_2457168
> > bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
> > depends on ARM64_AMU_EXTN
> > + select ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
> > default y
> > help
> > This option adds the workaround for ARM Cortex-A510 erratum 2457168.
> > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> > index 5db8f0619e4bc..f18683e56184b 100644
> > --- a/arch/arm64/kernel/cpu_errata.c
> > +++ b/arch/arm64/kernel/cpu_errata.c
> > @@ -381,6 +381,18 @@ static const struct arm64_cpu_capabilities arm64_repeat_tlbi_list[] = {
> > };
> > #endif
> >
> > +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
> > +static const struct arm64_cpu_capabilities arm64_repeat_amu_constcnt_list[] = {
> ^^^^^^
> There is nothing to repeat :)
>
> > +#ifdef CONFIG_ARM64_ERRATUM_2457168
> > + {
> > + /* Cortex-A510 r0p0-r1p1 */
> > + CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
> > + },
> > +#endif
> > + {}
> > +};
> > +#endif /* CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT */
> > +
> > #ifdef CONFIG_CAVIUM_ERRATUM_23154
> > static const struct midr_range cavium_erratum_23154_cpus[] = {
> > MIDR_ALL_VERSIONS(MIDR_THUNDERX),
> > @@ -916,14 +928,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2)
> > },
> > #endif
> > -#ifdef CONFIG_ARM64_ERRATUM_2457168
> > +#ifdef CONFIG_ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT
> > {
> > - .desc = "ARM erratum 2457168",
> > - .capability = ARM64_WORKAROUND_2457168,
> > + .desc = "Broken AMU AMEVCNTR01 (const counter)",
> > + .capability = ARM64_WORKAROUND_BROKEN_AMU_CONSTCNT,
> > .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
> > -
> > - /* Cortex-A510 r0p0-r1p1 */
> > - CAP_MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1)
>
> I think it should be
>
> CAP_MIDR_RANGE_LIST(amu_broken_constcnt_cpus)
True, that's more appropriate here.
Thanks
---
BR
Beata
>
> where amu_broken_constcnt_cpus is
>
> static const struct midr_range amu_broken_constcnt_cpus[] = {
> #ifdef CONFIG_ARM64_ERRATUM_2457168
> /* Cortex-A510 r0p0-r1p1 */
> MIDR_RANGE(MIDR_CORTEX_A510, 0, 0, 1, 1),
> #endif
> {}
> };
>
> so in the next patch you would add new entry
>
> #ifdef CONFIG_ARM64_ERRATUM_3821522
> /* Cortex-A725 r0p0 - r0p2 */
> MIDR_RANGE(MIDR_CORTEX_A725, 0, 0, 0, 2),
> #endif
>
>
> Cheers
> Vladimir
>
next prev parent reply other threads:[~2026-10-01 8:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 15:42 [PATCH v3 0/2] arm64: errata: Share broken AMU constant-counter handling Beata Michalska
2026-09-29 15:42 ` [PATCH v3 1/2] arm64: errata: Factor out broken AMU const counter cap Beata Michalska
2026-09-30 9:21 ` Vladimir Murzin
2026-10-01 8:50 ` Beata Michalska [this message]
2026-09-29 15:42 ` [PATCH v3 2/2] arm64: errata: Add Cortex-A725 erratum 3821522 workaround Beata Michalska
2026-09-30 9:27 ` Vladimir Murzin
2026-10-01 8:51 ` Beata Michalska
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