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Best regards, Richard Cheng. > cl_flush() and sb() compile to empty functions on aarch64, making > mem_flush() a silent no-op and leaving CMT/CAT tests operating on > unflushed state. > > Add "dsb sy" for sb(), ARM requires a DSB whose access type covers both > loads and stores. > > For cl_flush(), "dc civac" only reaches the Point of Coherency, on > ARM MPAM systems the SLC lies past the PoC and may be a NOP on coherent > platforms. Instead, dirty each cacheline with a store so that > mem_flush's full-buffer sweep evicts lines from the SLC via LRU > pressure. > > Signed-off-by: Richard Cheng > --- > Changes since v3: > - cl_flush(): replace "dc civac" with a dirty store. dc civac only > cleans to the Point of Coherency, so it does not reach the SLC > where MPAM cache portions are enforced. Rely on LRU eviction from > mem_flush()'s full-buffer sweep instead. > > tools/testing/selftests/resctrl/fill_buf.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c > index b9fa7968cd6e..eae0262fe265 100644 > --- a/tools/testing/selftests/resctrl/fill_buf.c > +++ b/tools/testing/selftests/resctrl/fill_buf.c > @@ -27,6 +27,9 @@ static void sb(void) > #if defined(__i386) || defined(__x86_64) > asm volatile("sfence\n\t" > : : : "memory"); > +#elif defined(__aarch64__) > + asm volatile("dsb sy\n\t" > + : : : "memory"); > #endif > } > > @@ -35,6 +38,14 @@ static void cl_flush(void *p) > #if defined(__i386) || defined(__x86_64) > asm volatile("clflush (%0)\n\t" > : : "r"(p) : "memory"); > +#elif defined(__aarch64__) > + /* > + * Dirty the cache line with a store. As mem_flush() sweeps > + * the full test buffer (sized larger than the SLC), cache pressure > + * evicts lines from the SLC via LRU replacement. > + */ > + asm volatile("strb wzr, [%0]\n\t" > + : : "r"(p) : "memory"); > #endif > } > > -- > 2.43.0 >