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Thu, 1 Oct 2026 16:30:44 +0000 Date: Thu, 1 Oct 2026 11:30:34 -0500 From: Frank Li To: Jeff Barnes Cc: linux-pci@vger.kernel.org, minghuan.Lian@nxp.com, mingkai.hu@nxp.com, roy.zang@nxp.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, Zhiqiang.Hou@nxp.com, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] Revert "PCI: layerscape: Change default error response behavior" Message-ID: References: <0FEA6868-5A7C-4955-9FBB-BE9A1AE8D3F7@getmailspring.com> <20261001153323.1965074-1-jeffbarnes@linux.microsoft.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261001153323.1965074-1-jeffbarnes@linux.microsoft.com> X-ClientProxiedBy: CYXPR03CA0009.namprd03.prod.outlook.com (2603:10b6:930:d0::7) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|AS8PR04MB9045:EE_ X-MS-Office365-Filtering-Correlation-Id: 2cc219e2-0c43-4506-9a17-08df1fd95703 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|19092799006|366016|1800799024|376014|7416014|18002099003|22082099003|4143699003|6133799003|3023799007|10067099003|56012099006|11063799006; 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Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > This reverts commit 84d897d69938 > ("PCI: layerscape: Change default error response behavior"). > > The Layerscape PCIe driver programs the DesignWare > AMBA_ERROR_RESPONSE_DEFAULT register at offset 0x8d0 with 0x9401. > > For AXI, the documented default with AMBA_ERROR_RESPONSE_GLOBAL cleared > returns OKAY with all-ones data for errors on non-posted requests. > Setting AMBA_ERROR_RESPONSE_GLOBAL causes an AXI error response instead, > with AMBA_ERROR_RESPONSE_MAP selecting SLVERR or DECERR for individual > PCIe completion errors. > > The value 0x9401 sets AMBA_ERROR_RESPONSE_GLOBAL and maps Unsupported > Request, Completer Abort, and Completion Timeout to SLVERR. > > A PCI configuration access can race with the link going down after > dw_pcie_other_conf_map_bus() checks the link but before > pci_generic_config_read() performs the MMIO access. If the transaction > results in a Completion Timeout, the Layerscape error response setting > propagates it to AXI as SLVERR, resulting in an asynchronous SError and > kernel panic. > > Reproduce the race by obtaining the configuration-space mapping while > the link is up, then disabling the link from another CPU immediately > before performing the MMIO configuration read. > > With the error response override enabled, the overlapping configuration > read results in an asynchronous SError and kernel panic. With the > DesignWare default behavior restored, the same test returns 0xffffffff. > AER reports a non-fatal Completion Timeout, and no SError or kernel > panic occurs. > > Restore the documented DesignWare default error response behavior so a > failed non-posted PCIe transaction does not become a fatal AXI error. > > Fixes: 84d897d69938 ("PCI: layerscape: Change default error response behavior") > Cc: stable@vger.kernel.org > Signed-off-by: Jeff Barnes > --- should be here, maintainer should can handle this for you. Reviewed-by: Frank Li . > Changes in v2: > - Change the subject to identify this as a revert, as requested by > Frank Li. > - Document the DesignWare AMBA_ERROR_RESPONSE_DEFAULT behavior and > decode the 0x9401 setting used by Layerscape. > - Clarify that the setting propagates Completion Timeout as AXI SLVERR > rather than causing the underlying PCIe transaction failure. > > --- > drivers/pci/controller/dwc/pci-layerscape.c | 12 ------------ > 1 file changed, 12 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c > index 14d6ac4fc53f..d333f1ae8a41 100644 > --- a/drivers/pci/controller/dwc/pci-layerscape.c > +++ b/drivers/pci/controller/dwc/pci-layerscape.c > @@ -28,8 +28,6 @@ > > /* PEX Internal Configuration Registers */ > #define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */ > -#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ > -#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ > > /* PF Message Command Register */ > #define LS_PCIE_PF_MCR 0x2c > @@ -103,14 +101,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) > iowrite32(val, pci->dbi_base + PCIE_STRFMR1); > } > > -/* Forward error response of outbound non-posted requests */ > -static void ls_pcie_fix_error_response(struct ls_pcie *pcie) > -{ > - struct dw_pcie *pci = pcie->pci; > - > - iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); > -} > - > static u32 ls_pcie_pf_lut_readl(struct ls_pcie *pcie, u32 off) > { > if (pcie->big_endian) > @@ -180,8 +170,6 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > struct ls_pcie *pcie = to_ls_pcie(pci); > > - ls_pcie_fix_error_response(pcie); > - > dw_pcie_dbi_ro_wr_en(pci); > ls_pcie_clear_multifunction(pcie); > dw_pcie_dbi_ro_wr_dis(pci); > -- > 2.43.0 >