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Thu, 1 Oct 2026 13:22:44 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Thu, 1 Oct 2026 13:22:42 -0700 Date: Thu, 1 Oct 2026 13:22:40 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , , Thomas Gleixner , Radu Rendec , Bjorn Helgaas , , , "Greg Kroah-Hartman" , , "Danilo Krummrich" , Subject: Re: [PATCH v11 13/16] iommu/arm-smmu-v3: Implement pm_runtime & system sleep ops Message-ID: References: <20260929034510.2023173-1-praan@google.com> <20260929034510.2023173-14-praan@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260929034510.2023173-14-praan@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231F:EE_|LV0PR12MB243158:EE_ X-MS-Office365-Filtering-Correlation-Id: 6069da64-a309-4036-a7b5-08df1ff9cde1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|376014|7416014|23010399003|1800799024|56012099006|6133799003|11063799006|4143699003|10067099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: /joHKHcVocduuhZZ4Mr+NO+05zxdWqnpFYLy+SyQELNicRWh1jHHUqV9ec3cVCMyfgiBN/Id/w+eYAbaPhoqQajIXONZ3zFBFWX4+3pg0PMdHjFNKyAuLeSj16K3DFA/dFTMBwuzcq8ypVylUkZcJpx3+ykDtYPHAxBjP4esizlPg6i0mMAc/iELbfNEIGkCMLsIcH9v+RjtoWdiNl93oUvbr6KiNgyklLPvASMcy1tWOBEpNoiAcb99eIprCI749bFgVLYqe09B45Y1Ek0KIFsPP2QL66JfochG+0TcfCjUjbq4VuyqqTFvW/SSLsk7DX9Qq38r8eK0CT5LgIIW+8RnZ4JC94O68YpF+x9d8CpN9fdDyUEMOMi//37IpU8NTYt+qbe+0B3oGK/9k74HWGJ2j8zavQWG8TIT1/0vKKRVL4aRFNboEHzmwHfiw5XF X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2026 20:23:07.1076 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6069da64-a309-4036-a7b5-08df1ff9cde1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV0PR12MB243158 Just some small things from a quick scan: On Tue, Sep 29, 2026 at 03:45:07AM +0000, Pranjal Shrivastava wrote: > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 0a841441cc44..d0a3d497915c 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -663,11 +663,14 @@ arm_smmu_make_cmd_tlbi(enum arm_smmu_cmdq_opcode op, u16 asid, u16 vmid) [...] > +#define RPM_AUTOSUSPEND_DELAY_MS 15 > + > struct arm_smmu_ll_queue { > union { > u64 val; > @@ -1234,6 +1237,18 @@ int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, > bool sync); > bool arm_smmu_erratum_repeat_tlbi_cfgi(void); > > +/* > + * Lockless pre-check to test if the SMMU is actively powered. > + * Races with concurrent suspend are benign: the cmpxchg loop in > + * arm_smmu_cmdq_issue_cmdlist() acts as the true commit point. > + * If we lose the race, that loop observes Q_STOP == 1 and safely > + * drops the command. If we win, the suspend thread waits for us. > + */ > +static inline bool arm_smmu_is_active(struct arm_smmu_device *smmu) > +{ > + return !Q_STOP(READ_ONCE(smmu->cmdq.q.llq.prod)); > +} Move these to the patch that uses it? > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 89a4e756ff17..e127e3be3a6b 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -29,6 +29,7 @@ > #include > #include > #include > +#include > #include > #include > > @@ -119,6 +120,45 @@ static const char * const event_class_str[] = { > static int arm_smmu_alloc_cd_tables(struct arm_smmu_master *master); > static bool arm_smmu_ats_supported(struct arm_smmu_master *master); > > +/* Runtime PM helpers */ > +__maybe_unused static int arm_smmu_rpm_get(struct arm_smmu_device *smmu) > +{ > + int ret; > + > + if (!pm_runtime_enabled(smmu->dev)) > + return 0; > + > + ret = pm_runtime_resume_and_get(smmu->dev); > + if (ret < 0) { > + dev_err(smmu->dev, "failed to resume device: %d\n", ret); > + return ret; > + } > + > + return 0; > +} > + > +__maybe_unused static bool arm_smmu_rpm_get_if_active(struct arm_smmu_device *smmu) > +{ > + if (!pm_runtime_enabled(smmu->dev)) > + return true; > + > + return pm_runtime_get_if_active(smmu->dev) > 0; > +} > + > +__maybe_unused static void arm_smmu_rpm_put(struct arm_smmu_device *smmu) > +{ > + int ret; > + > + if (!pm_runtime_enabled(smmu->dev)) > + return; > + > + ret = pm_runtime_put_autosuspend(smmu->dev); > + > + /* -EAGAIN & -EBUSY aren't failures */ > + if (ret < 0 && ret != -EAGAIN && ret != -EBUSY) > + dev_err(smmu->dev, "failed to suspend device: %d\n", ret); > +} Ditto > +static int __maybe_unused arm_smmu_runtime_suspend(struct device *dev) [...] > + /* Wait for the last committed owner to reach the hardware */ > + while (atomic_read(&cmdq->owner_prod) != target && timeout) { > + udelay(1); > + timeout--; > + } > + > + /* > + * Entering suspend implies no active clients. A timeout here > + * indicates a fatal CMDQ lockup or hardware stall. We proceed > + * anyway to prioritize memory safety (avoiding stale TLBs) > + */ > + if (!timeout) > + dev_err(smmu->dev, "cmdq owner wait timeout, (check runtime PM + devlinks)\n"); > + > + /* Wait for cmdq->lock == 0 to ensure last CMDQ_CONS_REG is written */ > + timeout = ARM_SMMU_SUSPEND_TIMEOUT_US; > + while (atomic_read(&cmdq->lock) != 0 && timeout) { > + udelay(1); > + timeout--; > + } > + > + /* Timing out here implies misconfigured Runtime PM or broken devlinks */ > + if (!timeout) > + dev_err(smmu->dev, "cmdq lock != 0, forcing suspend. Polling CPUs may fault.\n"); Maybe a small helper that takes: read pointer, target, print? > + /* Wait for pending gerror handlers */ > + synchronize_irq(smmu->combined_irq ? smmu->combined_irq : smmu->gerr_irq); Both might be 0? Nicolin