Re: [PATCH] i2c: designware: size the RX FIFO threshold to the queued transfer

[Andy Shevchenko <andriy.shevchenko@linux.intel.com>]

On Sun, Sep 20, 2026 at 04:56:47AM +0530, Navon John Lukose wrote:
> i2c_dw_xfer_msg() leaves DW_IC_RX_TL at the 0 that i2c_dw_configure_mode()
> writes, so the controller raises RX_FULL once per received byte. Program
> RX_TL from the reads already queued, capped at half the FIFO until the last
> message is queued, so there is room for the rest.
> 
> On an Arrow Lake-H LPSS core with rx_fifo_depth 32, a 22-byte HID report
> costs 2.00 interrupts instead of 21.43, and a 452-byte descriptor 0.14
> interrupts per byte instead of 1.64. Mean HIDIOCGINPUT latency rises from
> 2522 to 3268 us; holding /dev/cpu_dma_latency at 0 removes 94% of that.

Nobody will go with 0 in cpu_dma_latency. It basically kills the idea of CPU
power states. If you need a dynamic run-time PM QoS, patch the HID subsystem to
make those when they want to heavily communicate with the HW. There is also the
issue of the interrupt locality. Can you try to make that first and see how
much power saving you will get?

-- 
With Best Regards,
Andy Shevchenko