Re: [PATCH 2/2] arm64: dts: qcom: nord: add CoreSight debug nodes

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

On Tue, Sep 22, 2026 at 06:14:09PM +0800, Jie Gan wrote:
> 
> On 9/22/2026 6:08 PM, Shawn Guo wrote:
> > From: Jie Gan <jie.gan@oss.qualcomm.com>
> > 
> > Add the CoreSight trace topology for the Qualcomm Nord SoC: CTCU, STM,
> > TPDM/TPDA sources and aggregators, funnels, replicators, TMC ETR/ETF
> > sinks, TNoC/ITNoC nodes and per-subsystem CTIs. This wires up trace
> > sources for SOCCP, BCV/IMH/DPM, GCC, QM, DL_NOC, the CDSP NSP0-3
> > clusters, DLMM, EVA, MDSS0/1, LPASS and the AOSS SWAO priority TPDMs,
> > plus the DDR0-3 channel and LLCC TPDMs, all funneled through the
> > tn_ag aggregator into the main CoreSight funnel and out to the AOSS
> > sink.
> > 
> > Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
> > Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> > ---
> >   arch/arm64/boot/dts/qcom/nord.dtsi | 3540 ++++++++++++++++++++++++++--
> >   1 file changed, 3314 insertions(+), 226 deletions(-)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> > index 926ccf3bbe4e..3e4fbacc2eb3 100644
> > --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> > @@ -345,6 +345,18 @@ domain_ss3: domain-sleep-0 {
> >   		};
> >   	};
> > +	eud-sink {
> > +		compatible = "arm,coresight-dummy-sink";
> > +
> > +		in-ports {
> > +			port {
> > +				eud_in: endpoint {
> > +					remote-endpoint = <&aoss_rep0_out1>;
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> >   	firmware: firmware {
> >   		scm {
> >   			compatible = "qcom,scm-nord",
> > @@ -372,6 +384,20 @@ cpu_perf: protocol@13 {
> >   		};
> >   	};
> > +	hpass-stm {
> > +		compatible = "arm,coresight-dummy-source";
> > +		label = "hpass_stm";
> > +		arm,static-trace-id = <25>;
> > +
> > +		out-ports {
> > +			port {
> > +				lpass_stm_out: endpoint {
> > +					remote-endpoint = <&lpass_tn_in18>;
> > +				};
> > +			};
> > +		};
> > +	};
> > +
> >   	memory@80000000 {
> >   		device_type = "memory";
> >   		/* Size will be updated by bootloader */
> > @@ -1900,236 +1926,3178 @@ tlmm: pinctrl@f100000 {
> >   			wakeup-parent = <&pdc>;
> >   		};
> > -		apps_smmu_0: iommu@15a00000 {
> 
> Hi Shawn,
> 
> Thanks for helping post.
> 
> This irrelevant patch diff can be avoided with git config:
> git config diff.algorithm histogram.
> 
> As Coresight patch is large, better patch diff format helps review much
> easier.

Ah, thanks for the tip, Jie! Just set git config up as suggested. The
diff will look cleaner for the future versions.

Shawn