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Tue, 22 Sep 2026 15:39:06 -0700 Date: Tue, 22 Sep 2026 15:39:04 -0700 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , , , , Jean-Philippe Brucker Subject: Re: [PATCH v8 10/25] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver Message-ID: References: <20260922131259.2975334-1-smostafa@google.com> <20260922131259.2975334-11-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260922131259.2975334-11-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000013C:EE_|CY5PR12MB6384:EE_ X-MS-Office365-Filtering-Correlation-Id: f1d5748e-ea1e-4efa-d00e-08df18fa5e5e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|7416014|23010399003|6133799003|22082099003|18002099003|3023799007|11063799006|10067099003|56012099006|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: juHhOFJJ+oEyFzZtJn95p2InWRJLJlsMoDHNif/X6Lu77tPLd26UWTX0jzElus2r0nUtNS6NhxJNiCOQ9vmOkREtmbVbIq7TRQPZEepaB/TQGeV0OGsxM33M7UNNxwhh36EnJ36IS/FN5cszx/m0hDWQFEDWERwhP4tMuUdXAYcWPGixfctc2ATAt7cQBSWhss5otOQ8CQKKP1BEDA5ZQSiosimTS86arJ9OnILiJ7eE0HCArziDoKRcfOPpLdW3cBKZ/qA1OCSvKjllyfkjwMxPZzHdEQZo5Qm+rZD76mkSi+9WB1REc2WQaUPGH6lTAxvo8JWoDgT5xIWJyRBvojRx69hTy/H+8jReUPvgifxsGbBuAxMt/86qade5lAK0L/5jjjnP400TyOArUlSlgcRY3FCaUVin0pRti8Vhachg3jQaZuNnJYnC9EddWmzn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Sep 2026 22:39:31.2389 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f1d5748e-ea1e-4efa-d00e-08df18fa5e5e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000013C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6384 On Tue, Sep 22, 2026 at 01:12:43PM +0000, Mostafa Saleh wrote: > From: Jean-Philippe Brucker > > Add the skeleton for an Arm SMMUv3 driver at EL2. > > The driver rely on an array of SMMUv3s on the system, where at s/rely/relies > +++ b/drivers/iommu/arm/Kconfig > @@ -141,3 +141,15 @@ config QCOM_IOMMU > select ARM_DMA_USE_IOMMU > help > Support for IOMMU on certain Qualcomm SoCs. > + > +config ARM_SMMU_V3_PKVM > + bool "ARM SMMUv3 support for protected Virtual Machines" > + depends on KVM && ARM_SMMU_V3=y Should it depend on OF? > + help > + Enable a SMMUv3 driver in the KVM hypervisor, to protect VMs against s/a SMMUv3/an SMMUv3 > +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h > @@ -0,0 +1,31 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +#ifndef __KVM_ARM_SMMU_V3_HYP_H > +#define __KVM_ARM_SMMU_V3_HYP_H > + > +#include > + > +/* > + * Parameters from the trusted host: > + * @mmio_addr base address of the SMMU registers > + * @mmio_size size of the registers resource Are these still in the host's physical address space or guest's? If it's still "host" (though trusted), what's different from the ioaddr in the main driver? > +size_t __ro_after_init kvm_hyp_arm_smmu_v3_count; > +struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus; Should kvm_hyp_arm_smmu_v3_smmus be __ro_after_init as well? > + > +#define for_each_smmu(smmu) \ > + for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \ > + (smmu) != &kvm_hyp_arm_smmu_v3_smmus[kvm_hyp_arm_smmu_v3_count]; \ > + (smmu)++) "smmu" sounds too generic. Maybe for_each_pkvm_smmu? > +/* Called while is the host is still trusted. */ > +static int smmu_init(void) s/while is/while > +/* Shared with the kernel driver in EL1 */ > +struct pkvm_iommu_ops smmu_ops = { > + .init = smmu_init, > + .host_stage2_idmap = smmu_host_stage2_idmap, Can we add a "pvkm_arm_smmu_" prefix for the ops and functions here? Nicolin