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Tue, 22 Sep 2026 18:43:46 -0700 Date: Tue, 22 Sep 2026 18:43:44 -0700 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v8 12/25] iommu/arm-smmu-v3-kvm: Probe SMMU HW Message-ID: References: <20260922131259.2975334-1-smostafa@google.com> <20260922131259.2975334-13-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260922131259.2975334-13-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF00000009:EE_|DM4PR12MB8500:EE_ X-MS-Office365-Filtering-Correlation-Id: b18d4476-eefe-47b8-b0c7-08df1914290e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|82310400026|23010399003|36860700016|22082099003|18002099003|56012099006|4143699003|11063799006|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Pc2ov8xyjg68MpM7otGHjZ9atakZAdYAxtr5mmmp3pj7t/b2X4b6SY7+Wcq1QaMUchai4vtd8xiG1x1zMT3Byj8Lun5psOJKD+eYuIM3QBHbOlsOBpVeIXSTMUKKJU/NB45nTBuiq0haiesWXzWnonue3odiCItEUePo4wqEmsZdgRRNQtaRiVWnwhKWewEYPLBJ7imqcLKkalOI2UM5WcaJnDy+UxqEj0DvlYrqCsRrJ2c/wNvM5oFBzT8ESF8sKBYoKmMQArBxFxgMeCMrQOPfYfseN0cfcfSiltcMj7S5evqAlYE/xRFgjL1KnBNXTItKH2uHeWCXCjdIzSKDEJ7D0jlh6BsMtVjaQSHCf6c1SYFBNKImXx1U1xS426FpkG00TNmF8WtEXyRpLaFskAYIwIik1YgvfcqCJEwKlMqG7Z8GJYrQ2lkNh5q4AZn+ X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Sep 2026 01:44:08.7001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b18d4476-eefe-47b8-b0c7-08df1914290e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF00000009.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8500 On Tue, Sep 22, 2026 at 01:12:45PM +0000, Mostafa Saleh wrote: > +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3-hyp.h > @@ -11,6 +11,9 @@ > * > * Other members are filled and used at runtime by the SMMU driver. > * @base Virtual address of SMMU registers > + * @oas PA size > + * @pgsize_bitmap Supported page sizes > + * @sid_bits Max number of SID bits supported > */ Some of them belongs to one of the prior patches. And, if we are going to list them all, could we do in kdoc style? > +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c > @@ -29,6 +29,47 @@ static void smmu_deinit_device(struct hyp_arm_smmu_v3_device *smmu) > smmu->base = NULL; > } > > +/* > + * Mini-probe and validation for the hypervisor. > + */ > +static int smmu_probe(struct hyp_arm_smmu_v3_device *smmu) > +{ > + u32 reg; > + > + if (!(smmu->features & ARM_SMMU_FEAT_COHERENCY)) > + return -EINVAL; Does this need to check IDR0.COHACC? If not, an inline note that explains why? > + > + reg = arm_smmu_idr0_probe(smmu); > + > + if (!(FIELD_GET(IDR0_TTF, reg) & IDR0_TTF_AARCH64)) > + return -ENXIO; > + > + if (!(smmu->features & (ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE))) > + return -ENXIO; > + > + reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); > + if (reg & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET | IDR1_REL)) > + return -EINVAL; > + > + smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); > + /* Follows the kernel logic */ > + if (smmu->sid_bits <= STRTAB_SPLIT) > + smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; The IDR1 reg guard and sid_bits can be shared with the main driver. Maybe add an arm_smmu_device_idr1_probe()? > + > + arm_smmu_idr3_probe(smmu); > + > + arm_smmu_idr5_probe(smmu); > + if (!smmu->oas) > + smmu->oas = 48; The truncation can be shared with the main driver too? > @@ -43,8 +84,14 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_device *smmu) > return ret; > > smmu->base = (void __iomem *)haddr; > + ret = smmu_probe(smmu); > + if (ret) > + goto out_ret; > > return 0; > +out_ret: > + smmu_deinit_device(smmu); Nit: out_deinit Nicolin