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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f986e465sm11885603c88.9.2026.09.24.01.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Sep 2026 01:50:20 -0700 (PDT) Date: Thu, 24 Sep 2026 16:50:13 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa Subject: Re: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Message-ID: References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> <20260924-nords_dprx-v2-1-fa4364e087ef@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260924-nords_dprx-v2-1-fa4364e087ef@oss.qualcomm.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAzNyBTYWx0ZWRfX1Wcgc07DSRax 6kxA3xPhmrhx2LJOK4oVNpUjb87ZjDvJ9UVLNlVaPgUkKNN8miOQMGXPo8bd7djmsBgIL1Nzmhp Is7dOZJZmuA6VdAE6mDz1d79zPSWxT0= X-Proofpoint-ORIG-GUID: C_iwh8JQk0nuEdGo4QFpg8bXmf5KPMh6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAzNyBTYWx0ZWRfX0GqtRwprJ9Rm 87tpes+9fsN5aCDzCc8p3soXgVZpm0BGp2PnBEBnIr7dhcfZ84jPqKd5QD09R2Ups6TmzovrGVq t7qm2L5oRtttD5FyrB4SY+4TFw4ell+NzH1nEAktE4MA7e0s5p7+Jws8xhtX8IRKBumYcT2ivg1 R2jP8gEVOceTbdM+wl7CwFiTmk0n4iJOuXA8GZkuGRMFSeX9YFpxDo9h+aqQLC1VVyGqpgblx6y VC7gZZy/KMK8llWhiZFt6uso1WwWhais4wK5WbZ9l2gE+TAZ1IWyw4ko8hzE7A8Xcb9QC038/iy btHyi10fZex53O6u4njuwhqbS1pBLOoH2LHfoiBF63SfcC5zykPrKKCL39pD5iNFzgQ5qrXfAWG ASm0CXvoDuEmZt1WHlDgw/VwsZSsRr6hXn8Yw3lhgOoz1DIjQxsXi+15+rrIXn7KwsP74/sAgqT m3RLpB7K/hKWk1zNtWg== X-Authority-Analysis: v=2.4 cv=a6SlZkSF c=1 sm=1 tr=0 ts=6ab4e453 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=q38Eq4LkVyZCF8x0k14A:9 a=CjuIK1q_8ugA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-GUID: C_iwh8JQk0nuEdGo4QFpg8bXmf5KPMh6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 spamscore=0 clxscore=1015 malwarescore=0 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240037 On Thu, Sep 24, 2026 at 12:51:31AM +0530, Taniya Das wrote: > On some PLLs the PLL_ALPHA_VAL register has been increased to 28 bits to > carry the fractional word at a finer resolution, for example the > ZONDA_OLE instances on the Qualcomm Nord DPRX. The alpha-PLL core, > however, derives the ALPHA_VAL width solely from the register-map layout > and can only express 16 or 40 bits, so it programs and reads back the > 28-bit configuration at the wrong scale on both the set_rate/slew and > recalc_rate paths, making the PLL lock to and report the wrong rate. > > Add a way to identify the wider register: an optional alpha_width field > in struct clk_alpha_pll that, when non-zero, supersedes the > register-derived width. This feeds pll_alpha_width(), so the recalc_rate > and round_rate math scale the fractional word correctly, and the Zonda > set_rate L-adjust MSB check is derived from the active width instead of > a hardcoded BIT(15). PLLs that leave the field zero retain the previous > behaviour. > > Reviewed-by: Abel Vesa > Signed-off-by: Taniya Das Reviewed-by: Shawn Guo