From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Taniya Das <taniya.das@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: qcom: gcc: Fix GPLL enable register offset for Nord SoC
Date: Thu, 24 Sep 2026 17:46:16 +0800 [thread overview]
Message-ID: <arTxaIIDkomvxfWp@QCOM-aGQu4IUr3Y> (raw)
In-Reply-To: <20260924-nord_gcc_offset_fix-v1-1-230ffad2dae9@oss.qualcomm.com>
On Thu, Sep 24, 2026 at 03:09:56PM +0530, Taniya Das wrote:
> The GPLLs in the North-East, North-West and South-East global clock
> controllers on the Qualcomm Nord SoC were registered with a placeholder
> enable register offset of 0x0. As a result the shared PLL voting register
> was never programmed, leaving the PLLs' enable state uncontrolled.
>
> Point each GPLL at its actual GPLL_ENABLE register (0x57010 for the
> North-East and South-East controllers, 0x76008 for the North-West
> controller). Each PLL continues to select its own vote bit through
> enable_mask.
>
> Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
next prev parent reply other threads:[~2026-09-24 9:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 9:39 Taniya Das
2026-09-24 9:46 ` Shawn Guo [this message]
2026-09-24 11:35 ` Abel Vesa
2026-09-25 12:17 ` Konrad Dybcio
2026-09-25 16:43 ` Bjorn Andersson
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