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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZUuxc2ZAKlbPJXzUGmTxDQG8w6DiKxAdpfrBMJuubcx5srJojuXl8GRV373SvbtxbedaKLP9a/eRo7/dOX1hCtbaCLIIsskloYGGh6kzrR1yHxKeRRoKFREb/l6iSYqqeyDpm/oK1Wujy3G24Hq6m1DaIuk1MgZJCxDapFMrhonTQlDDrqh8QTSdaFzMPctT0QAwEK1uuC6lfiOwJs/RvAR3+RC81ocQ+Gj5lSBW7uolUALSlzZkcZ11OElQrDMVvxGVSriXHKFL9PNg+jNq5VAzzORI172Aj4PFJ9IPl7BU76kyiVn63JCZ4t2QIx0D8Yph/lVYvcR+zRj/rg2YoRptYMde2zir6yw5f0s627JQN5qGy38fjazXRSSB36uqT/t7zZPqNz8j9jsdyQu1L4KSLRAOaORqwDS+a2FQzF6as90P5yJQ7mMRlBWYOfig X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 Sep 2026 19:03:03.0135 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4f472be-c3f2-44d9-7424-08df1b379ff0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CB.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6527 On Fri, Sep 25, 2026 at 03:15:29PM +0100, Kiryl Shutsemau wrote: > From: "Kiryl Shutsemau (Meta)" > > The command queue depth comes straight from the maximum the hardware > advertises in IDR1, which reaches megabytes of coherent DMA per queue. > A system with several SMMUv3 instances pays that per instance, and the > Tegra241 CMDQV pays it again for every VCMDQ it preallocates. > > Queue depth only bounds how many commands may be in flight before a sync. > A machine driving a handful of devices, or one with a tight memory budget, > has no use for the maximum, and no way to say so. > > Add cmdq_max_n_shift, a cap on the depth given as the log2 of the entry > count, the form the hardware itself takes in the LOG2SIZE field of > CMDQ_BASE. It defaults to the largest depth the driver allocates, so an > unset parameter changes nothing. Decide the depth in > arm_smmu_cmdq_max_n_shift(), which applies the parameter to the IDR1 > value, so the queue is allocated at the requested size. The Tegra241 CMDQV > sizes its VCMDQs from IDR1 itself, so route that through the same helper. > > Floor the request at one page worth of entries. Without the floor, a small > request trips the CMDQ_BATCH_ENTRIES check in arm_smmu_device_hw_probe() > and the SMMU fails to probe. The floor also costs nothing: coherent DMA is > page granular, so a shallower queue occupies the same memory as one that > fills the page. > > Assisted-by: LLM > Reviewed-by: Breno Leitao > Reviewed-by: Jason Gunthorpe > Signed-off-by: Kiryl Shutsemau (Meta) Reviewed-by: Nicolin Chen Tested-by: Nicolin Chen