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charset=us-ascii Content-Disposition: inline Linus, Please pull the latest perf/urgent Git tree from: git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-urgent-2026-09-27 for you to fetch changes up to 24b620729e53d978b3e425f55bc66efd3bab1f59: Perf events fixes: - Fixes for KVM guest PEBS virtualization (Sean Christopherson) - Fixes for various Intel PMUs related to PEBS data-source (Dapeng Mi) - Fix Intel Panther Cove event scheduling constraints (Dapeng Mi) - Fix Intel DMR/NVL OMR extra registers event scheduling (Dapeng Mi) - Rename two confusingly named PMU attributes (Dapeng Mi) - Fix a refcount leak in attach_perf_ctx_data() (Namhyung Kim) - Fix NULL pointer dereference crash in __perf_pmu_sched_task() (Puranjay Mohan) - Fix CPU-wide event scheduling (Puranjay Mohan) - Fix x86 LBR branch entry generation (Puranjay Mohan) Thanks, Ingo ------------------> Dapeng Mi (12): perf/x86/intel: Fix GRT PEBS load/store direction for latency events, to fix sample classification perf/x86/intel: Fix CMT PEBS load/store direction for latency events, to fix sample classification perf/x86/intel: Fix DKT PEBS load/store direction for latency events, to fix sample classification perf/x86/intel: Update arw_latency_data() mem-op direction handling perf/x86/intel: Remove incorrect LionCove PEBS data-source constraints perf/x86/intel: Remove incorrect Panther Cove PEBS data-source constraints perf/x86/intel: Fix Panther Cove PEBS data-source snoop states perf/x86/intel: Delete dead NVL PEBS data-source initcall perf/x86/intel: Constrain Panther Cove UOPS_DISPATCHED events to PMCs 0-3 perf/x86/intel: Fix precise OMR event scheduling for DMR/NVL perf/x86/intel: Rename DMR offcore_rsp attribute to offmodule_rsp perf/x86/intel: Rename NVL offcore_rsp attribute to offmodule_rsp Namhyung Kim (1): perf/core: Fix a refcount leak in attach_perf_ctx_data() Puranjay Mohan (3): perf/core: Fix NULL pmu_ctx passed to pmu->sched_task() perf/core: Run sched_task() for PMUs with only CPU-wide events perf/core: Fill branch entries with a single assignment Sean Christopherson (4): perf/x86/intel: Ensure KVM guest PEBS path doesn't set unwanted PERF_GLOBAL_CTRL bits perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU has PEBS isolation, to fix stuck PEBS_ENABLED perf/x86/intel: Don't pointlessly context switch DS_AREA (and PEBS config) if PEBS is unused perf/x86/intel: Make @data a mandatory param for intel_guest_get_msrs() arch/x86/events/amd/brs.c | 9 ++- arch/x86/events/amd/lbr.c | 16 +++--- arch/x86/events/intel/core.c | 131 +++++++++++++++++++++++++++++++++---------- arch/x86/events/intel/ds.c | 74 +++++++++++------------- arch/x86/events/intel/lbr.c | 65 +++++++++++---------- arch/x86/events/perf_event.h | 4 -- drivers/perf/arm_brbe.c | 2 +- include/linux/perf_event.h | 17 ------ kernel/events/core.c | 17 ++++-- 9 files changed, 196 insertions(+), 139 deletions(-)