From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7EE144611CF; Wed, 30 Sep 2026 08:29:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790756947; cv=none; b=sT4s5r+AwynkKBD1rLNAK0mcCy1btEskbZwx9560rqHwAOV32222vcY3p0/wtWFcn7k+eTkweFDtB+RjfkwHaZZGwp4S6JO3TiHHkasYkkcxhxjwRHb4R83obK6K1OdKiTexHWcvSajCNaioCOKM6sFcS+q2BAjs3yw7vetoX8E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790756947; c=relaxed/simple; bh=qJaKz00fj7KxDc0CGeVJJ+tvs/tiUbxN90/yhOIRNLk=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rfuiSYEBD0eb4iK9pA3FlwQO+MyhoSEnKxx2wsnLAs7pB6g6oVpkvtoqWq9veKUcKA7k9qjasJHG17AOGmDFk+/HZVg4T3WmyT5A831QXu8vVdc3gjV84QEtOhq1UaJRxMsuaDEmrsI8QRKt8cctdss18kKUYGfQU9NGeEjORCo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aM+UxX3N; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aM+UxX3N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83F9E1F000FF; Wed, 30 Sep 2026 08:29:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790756946; bh=qJaKz00fj7KxDc0CGeVJJ+tvs/tiUbxN90/yhOIRNLk=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=aM+UxX3Nsf7rGPDSu7WqIGPpBgtIL9y6uXTb03PDTCRdL1BV2wsbPkB8Tc1POFQ+g 51T0NbnqKsbXyjol17cNTjMIthKpV4QHOKhpLoAMArFhGyGy5U8z4q5OKamMF9zplv E64LdT4GbWj5U6JvejiVIWyyw456gmiHaiAslm2NUxPoGoBpj4iSdU0dJxl7IMy5ep R+ZkuSIPi6I199YwCzkYLnduUoJbHo9emYfYyZ0fgN7ZZ859P7AL89ULIXsPL3pPMb 9IwqwlNUmF/A+OMOiTlnggN7wglFo9a0UAibUh8dYuTA/iOSxEcxqU4b8pfxd5EauH Y9vB6QTwHqddA== Date: Wed, 30 Sep 2026 10:29:03 +0200 From: Thierry Reding To: Mikko Perttunen Cc: David Airlie , Simona Vetter , Jonathan Hunter , Thierry Reding , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line Message-ID: References: <20260930-dalmore-fixes-dsi-reset-v1-1-58c9d12f5ebd@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="44hvupbkmw3pca6w" Content-Disposition: inline In-Reply-To: --44hvupbkmw3pca6w Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line MIME-Version: 1.0 On Wed, Sep 30, 2026 at 09:40:51AM +0200, Thierry Reding wrote: > On Wed, Sep 30, 2026 at 01:54:55PM +0900, Mikko Perttunen wrote: > > The DSI driver ignores the reset line if a power domain is configured. > > This was originally added to support Tegra210, where the power domain > > provider has to control the reset line -- at that time, older SoCs > > didn't have a power domain for DSI. Now, however, they do with the core > > power domain. > >=20 > > This happens to work on most systems due to DSI already being out of > > reset when booting the kernel, but on Tegra114 Dalmore, this is not the > > case and causes the system to hang during boot. > >=20 > > Ownership of the reset line is no longer a problem with reset > > acquire/release semantics, so control the DSI reset unconditionally > > from the DSI driver (possibly in addition to the power domain driver). > > The device tree bindings already require the reset and it is present > > on all platforms, so this is safe to do. >=20 > That seems backwards to me. The whole point of doing this via power > domains was because it's explicitly not safe to toggle that reset line > outside of the powergate switching sequence. >=20 > Also, the power domain code paths are supposed to work regardless of > whether the DSI was already out of reset or not. If that's not working > right now, I think that would qualify as a bug in the power domain code > rather than the DSI driver. >=20 > Shouldn't this be fixed at the powergate level? My recollection is that > DSI is tightly coupled to the display powergates, though it's been a > long time. Do we maybe need to reflect that in DT? There's a TODO in > tegra114.dtsi that seems to indicate that we're missing DIS and DISB > powergate implementations, so maybe that's where we should start to try > and resolve this. Looking at this a bit more, pd_core doesn't seem to make sense for DSI. Basically what that does, semantically, is claim that there's a power domain responsible for powering up and down the device, but in reality it doesn't to squat. Does the hang you observe go away if you remove the power-domains property for DSI? pd_core should probably be removed for both display controllers and HDMI as well. Probably also TSEC, though the TRM isn't clear about what power partition that's in (probably DISB because it's used primary for HDMI, which is in DISB as well). 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