From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDB713AAF60; Wed, 30 Sep 2026 08:47:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790758027; cv=none; b=CEbS2EpswMckwf7GZ3ei+ZiHiWpm1lb94xeOFT+/CRXtMrnYN987CZqiY1k3hexi6NapiYZONDipZaPY27ZS5+2q4r4RmGL1i+7cQ2jkWLHnMOe34m61gbWRCkI72hLT5XdlmB7In6fsAwxRoF7bFjMIKo1+9CAxNWL+ThOrt+M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790758027; c=relaxed/simple; bh=AkvUq0pC4ZvJyS3Jk4xgbCF+oh+bUEfwi3a4UPhs8tA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=r9KTsUZFDW8d23e22blurmMp0toGUU+wwkmmeB1fj4+zSUhL2KG5v9L+yVORSKZ3TJ35x0hT6rulYtPShpzWpnL3V7H3ClrwcrYZIe5089Z9aohVSNZnMw53uCt8pACjCcq7vUNkEsif/uoSd+NpWvgIBE2fBUv4F3exycaz1bg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=J9JsBKGj; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="J9JsBKGj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 589D21F00893; Wed, 30 Sep 2026 08:47:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790758024; bh=dXYx3+EiBk9/ho0dEeq/QLvZ8MeUmFOk1BYe/4MQKZY=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=J9JsBKGjgHoXeTcujl/ZvQ4JIhqK9A629I9OTXF7oiUBqn8WliL9TD7lg9Z/iIpYE ZHuDHIeAiCZ6d2a1uXjGBLIBkNimbztsI7gLcDVaG2qBY7moI1/QJHJoeAEjcj/9d9 4dbIu0E7PYaHo8QetQV3uJ5gkG8/7XOCBG1MAEc5E0Fr4oJrFWUNpxDnn1/e7Qsq8s Q1ibi8kcRQ0ocdLYm23xmdXvRnJ/TQF5d7Nu+5Ic6KRTrC6n+BsUQDpmp/W9hpwJHu iNHZXlfbiKyEayBXxpo4Il8ApOGSx1DwFnvXrWGJuT1DBfdgMIijPGqa4BWky620pF PMR+BN/0N6HLA== Date: Wed, 30 Sep 2026 10:47:02 +0200 From: Thierry Reding To: Svyatoslav Ryhel Cc: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Mikko Perttunen , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v1 3/6] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Message-ID: References: <20260930070535.47130-1-clamor95@gmail.com> <20260930070535.47130-4-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="w7pdjaspmarkr4mf" Content-Disposition: inline In-Reply-To: <20260930070535.47130-4-clamor95@gmail.com> --w7pdjaspmarkr4mf Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v1 3/6] dt-bindings: display: tegra: Document 8-bit CPU parallel interface MIME-Version: 1.0 On Wed, Sep 30, 2026 at 10:05:32AM +0300, Svyatoslav Ryhel wrote: > Document 8-bit CPU parallel MIPI DBI Type B interface provided by > Tegra20/30 SoCs display controller. >=20 > Signed-off-by: Svyatoslav Ryhel > --- > .../display/tegra/nvidia,tegra-8bit-cpu.yaml | 138 ++++++++++++++++++ > 1 file changed, 138 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidi= a,tegra-8bit-cpu.yaml >=20 > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra= -8bit-cpu.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,teg= ra-8bit-cpu.yaml > new file mode 100644 > index 0000000000000..f0dab608b2936 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-c= pu.yaml > @@ -0,0 +1,138 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-8bit-cpu.y= aml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nvidia Tegra DC based MIPI DBI Type B bridge > + > +maintainers: > + - Svyatoslav Ryhel > + > +description: The display controller in Tegra20/30 SoCs features an > + 8-bit SPI interface that closely resembles the MIPI DBI Type B > + protocol and is referred to as '8-bit CPU'. Each display controller > + provides two such interfaces, which can be used to send MIPI DCS > + commands to initialize and control the panel while image data is > + transmitted via 16/18/24-line RGB. > + > +properties: > + compatible: > + const: nvidia,tegra-8bit-cpu The description says that this is a feature of the display controller, so adding a new binding and compatible string for this is not the right move. This is all covered by the "nvidia,tegra{20,30}-dc" already, just need to extend that with whatever is new. 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