From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10FA93BFE4C; Wed, 30 Sep 2026 09:22:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790760179; cv=none; b=T0ch/edaWspAX3d2ufO3uqvg72WFSemkS0322kY+FnUR0K4t7CYA8kZDhQMkYMOplyD0buV96BDx/5HltBOkZzO3h1ikg91i6gpaiuxw1bypq/0xPGPvH5jLOpgzK7u/QAiGwx2H09g1voVyDvyV/0AwQGompZubCRNvHqeB20U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790760179; c=relaxed/simple; bh=5bykXwQFrecea4n/p/foXaV5dD52zoBJ8muDDo81Avc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=CcQiNwzp2d3TV6eijVrdQkUAmAIICSo8htmhKOWo/bBPY1VkhOQ8woqduOsfj8dN5aMjYyYpjOGqkEJ5KubuvbH9SVa8IWodZ0FfG+jOep74AkPrOSf7TaGJ95hIxIZG27EuEM1bV8yXXRBU7p2kZ3ZR5PHVxw2J7dvmfaVc9W0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e5djgav/; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e5djgav/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 04AC81F000FF; Wed, 30 Sep 2026 09:22:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1790760177; bh=X/x70JWMsn0GwooOf5u0/FT6WEHaSv2RtNgAbg9eDUE=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=e5djgav/nnv67NRjmVWS/jXi8pwQvITvBXT+Ib3W1g2p963qYfms2yoj5bprChMF/ 5m+KvMfJCC6+Juk08nbuBXptLKDUdb8Z3OnnB2Kg/5wX+GfnUaNMgPcDJfwkwlCl7H nJxHZ17t93KISpE7QLxl4r8w0f+Hf/HHRSFPhY78uynCHL38WhdunTvzqNMC3vr/3h krTAm9jMbPoEcjd5rx2Mt9tDILz7gqu7O400AjNex57XauSlP3WqyRcfQlH3sjBrCG a2kwHr80Avvgg/Zcr2n5kt1HSvqsjatra6a8lzTOFbLsNnsz+kuwDhrw81+iilW0rc 6ZXBCCEFFgPZg== Date: Wed, 30 Sep 2026 11:22:55 +0200 From: Thierry Reding To: Mikko Perttunen Cc: David Airlie , Simona Vetter , Jonathan Hunter , Thierry Reding , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line Message-ID: References: <20260930-dalmore-fixes-dsi-reset-v1-1-58c9d12f5ebd@nvidia.com> <8pr0OOFrTHeQTZiJatWz_Q@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="tm4xvg5k43shc5ai" Content-Disposition: inline In-Reply-To: <8pr0OOFrTHeQTZiJatWz_Q@nvidia.com> --tm4xvg5k43shc5ai Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH] drm/tegra: dsi: Unconditionally manage reset line MIME-Version: 1.0 On Wed, Sep 30, 2026 at 05:46:01PM +0900, Mikko Perttunen wrote: > On Wednesday, September 30, 2026 5:29=E2=80=AFPM Thierry Reding wrote: > > On Wed, Sep 30, 2026 at 09:40:51AM +0200, Thierry Reding wrote: > > > On Wed, Sep 30, 2026 at 01:54:55PM +0900, Mikko Perttunen wrote: > > > > The DSI driver ignores the reset line if a power domain is configur= ed. > > > > This was originally added to support Tegra210, where the power doma= in > > > > provider has to control the reset line -- at that time, older SoCs > > > > didn't have a power domain for DSI. Now, however, they do with the = core > > > > power domain. > > > >=20 > > > > This happens to work on most systems due to DSI already being out of > > > > reset when booting the kernel, but on Tegra114 Dalmore, this is not= the > > > > case and causes the system to hang during boot. > > > >=20 > > > > Ownership of the reset line is no longer a problem with reset > > > > acquire/release semantics, so control the DSI reset unconditionally > > > > from the DSI driver (possibly in addition to the power domain drive= r). > > > > The device tree bindings already require the reset and it is present > > > > on all platforms, so this is safe to do. > > >=20 > > > That seems backwards to me. The whole point of doing this via power > > > domains was because it's explicitly not safe to toggle that reset line > > > outside of the powergate switching sequence. >=20 > If you're referring to the MBIST workaround, unless I misremember, it=20 > doesn't mean the reset cannot be used outside the powergate sequence,=20 > just that it has to be used within in. It's not just the MBIST workaround, but the officially recommended way to powergate/ungate devices. Sure you could do whatever you want with the reset outside of that sequence, but that doesn't mean it's a great idea to do so. With runtime PM we can be reasonably sure that we're in a known-good state at this point, which is the only reason we could get away with doing this. That doesn't make it right, though. > > >=20 > > > Also, the power domain code paths are supposed to work regardless of > > > whether the DSI was already out of reset or not. If that's not working > > > right now, I think that would qualify as a bug in the power domain co= de > > > rather than the DSI driver. > > >=20 > > > Shouldn't this be fixed at the powergate level? My recollection is th= at > > > DSI is tightly coupled to the display powergates, though it's been a > > > long time. Do we maybe need to reflect that in DT? There's a TODO in > > > tegra114.dtsi that seems to indicate that we're missing DIS and DISB > > > powergate implementations, so maybe that's where we should start to t= ry > > > and resolve this. > >=20 > > Looking at this a bit more, pd_core doesn't seem to make sense for DSI. > > Basically what that does, semantically, is claim that there's a power > > domain responsible for powering up and down the device, but in reality > > it doesn't to squat. >=20 > Doesn't that reasoning apply for every device? Not necessarily. There might be devices that are truly only powered by the core domain. > Technically, pd_core=20 > corresponds to the core power rail. That only means it needs to be the top-level power domain, but it doesn't imply that it is the only power domain involved to make any particular device work. > DSI is powered from it.. we=20 > certainly haven't always had an expectation that the power domain=20 > provider handles resets for the device. Well, as evidenced by the issue you are observing, that expectation is indeed very much baked in. DSI is part of the DIS partition, which might be powered by the core partition, but the DIS partition also needs to control a bunch of clocks and resets associated with devices that are part of it. If you omit that DIS partition, then, yes, things are expected to not work because the clocks and resets are not handled at all. > On Tegra114 it looks like DSI indeed is in the DIS domain so that would= =20 > handle it, but on Tegra20/Tegra30 that isn't the case (even if those=20 > device seem to be working right now anyway). Tegra20 and Tegra30 also seem to be wrong, to be honest. If they work, then they probably only do by some happy accident. Evidently I wasn't paying enough attention at the time and was convinced it was all correct because of the Tested-bys. I'm now wondering how much testing was actually done for these. Once the display is turned off and back on (via framebuffer blank or DPMS), it shouldn't come up properly again. Well, except maybe if the disable and enable sequences are good enough to not need the reset in the middle. > > Does the hang you observe go away if you remove the power-domains > > property for DSI? pd_core should probably be removed for both display > > controllers and HDMI as well. Probably also TSEC, though the TRM isn't > > clear about what power partition that's in (probably DISB because it's > > used primary for HDMI, which is in DISB as well). >=20 > I'd expect it would go away since the reset code in the driver would=20 > activate then. Good, and that's the right thing in that case. Again, the power domains were introduced to specifically address the (clock/)reset/powergate sequence requirements. That's why the code uses the power domain code paths in a mutually exclusive way with the resets. Either the power domains take care of the entire power sequencing as recommended by the TRM, or it doesn't (in which case we fall back to the more brittle manual sequencing that we do). So I stand by what I said earlier: if there's no power domain handling the entirety of the DSI controller power sequencing, then the DT should not have a power-domains property for the DSI controllers. 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